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1. 发明授权

US08203562B1 Apparatus, system, and method for distributing work to integrated heterogeneous processors 有权
标题翻译：用于将工作分配到集成异构处理器的装置，系统和方法
公开(公告)号：US08203562B1
公开(公告)日：2012-06-19
申请号：US12243766
申请日：2008-10-01
申请人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
发明人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
IPC分类号： G06T15/00 , G06F15/16
CPC分类号： G06F15/16 , G06F9/5044 , G06T1/20 , G06T15/005 , G09G5/363 , G09G2330/021 , G09G2360/06 , Y02D10/22
摘要： An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.
摘要翻译：集成电路包括至少两种不同类型的处理器，诸如图形处理器和视频处理器。通常由两种不同类型的处理器支持至少一种操作。对于被调度的每个通常支持的操作，作出决定以确定将选择哪种类型的处理器来实现该操作。

2. 发明授权

US07466316B1 Apparatus, system, and method for distributing work to integrated heterogeneous processors 有权
标题翻译：用于将工作分配到集成异构处理器的装置，系统和方法
公开(公告)号：US07466316B1
公开(公告)日：2008-12-16
申请号：US11012390
申请日：2004-12-14
申请人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
发明人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
IPC分类号： G06F15/00 , G06F15/16 , G06F15/80 , G06F13/14 , G06F15/76 , G06F9/44 , G06T1/00 , G06T1/20 , G09G5/39 , G09G5/36
CPC分类号： G06F15/16 , G06F9/5044 , G06T1/20 , G06T15/005 , G09G5/363 , G09G2330/021 , G09G2360/06 , Y02D10/22
摘要： An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.
摘要翻译：集成电路包括至少两种不同类型的处理器，诸如图形处理器和视频处理器。通常由两种不同类型的处理器支持至少一种操作。对于被调度的每个通常支持的操作，作出决定以确定将选择哪种类型的处理器来实现该操作。

3. 发明授权

US07446773B1 Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler 有权
标题翻译：具有集成调度器的集成异构处理器的装置，系统和方法
公开(公告)号：US07446773B1
公开(公告)日：2008-11-04
申请号：US11012461
申请日：2004-12-14
申请人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
发明人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
IPC分类号： G06F15/00 , G06F15/16 , G06F15/80 , G06F13/14 , G06F15/76 , G06F9/44 , G06T1/00 , G06T1/20 , G09G5/39 , G09G5/36
CPC分类号： G06F15/16 , G06F9/4893 , G06F9/5044 , G06F9/505 , Y02D10/22 , Y02D10/24
摘要： An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or more different types of processors. The scheduler schedules operations on the different types of processors.
摘要翻译：集成电路包括至少两种不同类型的处理器。集成电路包括集成主机和相关调度器。两个或多个不同类型的处理器支持至少一个操作。调度器对不同类型的处理器进行调度。

4. 发明授权

US07898545B1 Apparatus, system, and method for integrated heterogeneous processors 有权
标题翻译：集成异构处理器的装置，系统和方法
公开(公告)号：US07898545B1
公开(公告)日：2011-03-01
申请号：US11012464
申请日：2004-12-14
申请人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
发明人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
IPC分类号： G06F13/14 , G06F15/16
CPC分类号： G06F9/5094 , G06F9/5044 , Y02D10/22
摘要： An integrated circuit includes at least two different types of processors. At least one operation is supported by both types of processors, which permits a commonly supported operation to be scheduled on either processor.
摘要翻译：集成电路包括至少两种不同类型的处理器。两种类型的处理器支持至少一种操作，这允许在任一处理器上调度通常支持的操作。

5. 发明授权

US07301542B1 System and method for filtering graphics data on scanout to a monitor 有权
标题翻译：将扫描的图形数据过滤到监视器的系统和方法
公开(公告)号：US07301542B1
公开(公告)日：2007-11-27
申请号：US10954548
申请日：2004-09-29
申请人： Michael Toksvig , Walter Donovan , Jonah M. Alben , Krishnaraj S. Rao , Stephen D. Lew
发明人： Michael Toksvig , Walter Donovan , Jonah M. Alben , Krishnaraj S. Rao , Stephen D. Lew
IPC分类号： G06T1/60 , G06T9/00 , G06T1/00
CPC分类号： G09G5/395 , G06T5/20 , G09G5/391 , G09G2340/02
摘要： A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.
摘要翻译：图形处理系统在扫描输出操作期间对过采样数据执行滤波。从过采样帧缓冲区中读取采样值，并在扫描期间进行滤波; 滤波后的颜色值（每像素一个）被提供给显示设备，而没有将经滤波的数据存储在帧缓冲器中的中间步骤。在一个实施例中，滤波电路包括被配置为从包含过采样数据的帧缓冲器读取对应于采样点的数据值的存储器接口; 以及滤波器，被配置为接收由所述存储器接口提供的数据值，以从所述数据值计算像素值，并且传输所述像素值以供显示设备显示，其中，所述滤波器在扫描输出操作期间计算所述像素值。

6. 发明授权

US06870542B2 System and method for filtering graphics data on scanout to a monitor 有权
标题翻译：将扫描的图形数据过滤到监视器的系统和方法
公开(公告)号：US06870542B2
公开(公告)日：2005-03-22
申请号：US10187111
申请日：2002-06-28
申请人： Michael Toksvig , Walter Donovan , Jonah M. Alben , Krishnaraj S. Rao , Stephen D. Lew
发明人： Michael Toksvig , Walter Donovan , Jonah M. Alben , Krishnaraj S. Rao , Stephen D. Lew
IPC分类号： G06T5/20 , G09G5/391 , G09G5/395 , G09G5/39
CPC分类号： G09G5/395 , G06T5/20 , G09G5/391 , G09G2340/02
摘要： A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.
摘要翻译：图形处理系统在扫描输出操作期间对过采样数据执行滤波。从过采样帧缓冲区中读取采样值，并在扫描期间进行滤波; 滤波后的颜色值（每像素一个）被提供给显示设备，而没有将经滤波的数据存储在帧缓冲器中的中间步骤。在一个实施例中，滤波电路包括被配置为从包含过采样数据的帧缓冲器读取对应于采样点的数据值的存储器接口; 以及滤波器，被配置为接收由所述存储器接口提供的数据值，以从所述数据值计算像素值，并且传输所述像素值以供显示设备显示，其中，所述滤波器在扫描输出操作期间计算所述像素值。

7. 发明授权

US09164766B1 System and method for hardware assisted stack 有权
标题翻译：硬件辅助堆栈的系统和方法
公开(公告)号：US09164766B1
公开(公告)日：2015-10-20
申请号：US11102189
申请日：2005-04-08
申请人： Aron L. Wong , Dennis K. Ma , Jonah M. Alben , Mark S. Krueger , Jeffrey J. Irwin
发明人： Aron L. Wong , Dennis K. Ma , Jonah M. Alben , Mark S. Krueger , Jeffrey J. Irwin
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/4401 , G06F9/5016 , G06F2209/509
摘要： Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.
摘要翻译：用于以硬件辅助堆栈的形式提供附加存储的方法和装置，其可由运行有限资源的环境的软件使用。作为示例，硬件辅助堆栈可以向在其有限的分配的地址空间内可访问的VBIOS代码提供额外的堆栈空间。

8. 发明申请

US20120212271A1 DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT 有权
标题翻译：双触发低能量FLIP-FLOP电路
公开(公告)号：US20120212271A1
公开(公告)日：2012-08-23
申请号：US13033426
申请日：2011-02-23
申请人： William J. DALLY , Jonah M. Alben , John W. Poulton , GE (Francis) Yang
发明人： William J. DALLY , Jonah M. Alben , John W. Poulton , GE (Francis) Yang
IPC分类号： H03K3/02
CPC分类号： H03K3/36 , H03K3/012 , H03K3/356121
摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
摘要翻译：本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。

9. 发明授权

US07586492B2 Real-time display post-processing using programmable hardware 有权
标题翻译：使用可编程硬件实时显示后处理
公开(公告)号：US07586492B2
公开(公告)日：2009-09-08
申请号：US11019414
申请日：2004-12-20
申请人： Duncan A. Riach , John M. Danskin , Jonah M. Alben , Michael A. Ogrinc , Anthony Michael Tamasi
发明人： Duncan A. Riach , John M. Danskin , Jonah M. Alben , Michael A. Ogrinc , Anthony Michael Tamasi
IPC分类号： G06F15/16 , G06F9/46 , G09G5/399
CPC分类号： G09G5/363 , G06F3/1431 , G06T15/005 , G09G5/001 , G09G5/393 , G09G5/395 , G09G5/399 , G09G2310/04 , G09G2360/125 , G09G2360/127
摘要： In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.
摘要翻译：在图形处理器中，渲染对象和后处理对象与可编程执行核共享对主处理器的访问。渲染对象从几何数据生成图像的碎片数据。后处理对象操作以从片段数据生成像素数据帧，并将像素数据存储在帧缓冲器中。与主处理器的操作并行，扫描引擎引擎读取先前产生的帧的像素数据，并将像素数据提供给显示设备。扫描引擎周期性地触发主处理器来操作后处理对象以产生下一帧。可以控制扫描输出引擎和后处理对象之间的时序，使得当扫描引擎引擎完成读取当前帧时，待显示的下一帧准备在帧缓冲器中。

10. 发明授权

US07355602B1 Surrogate stencil buffer clearing 有权
标题翻译：代理模板缓冲液清理
公开(公告)号：US07355602B1
公开(公告)日：2008-04-08
申请号：US10985699
申请日：2004-11-10
申请人： Mark J. Kilgard , Jonah M. Alben , Cass W. Everitt
发明人： Mark J. Kilgard , Jonah M. Alben , Cass W. Everitt
IPC分类号： G09G5/36
CPC分类号： G06T11/40
摘要： Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.
摘要翻译：使用代理模板缓冲液清除高效清除模板缓冲器的方法和装置。硬件寄存器跟踪自上次实际清除以来模板缓冲区的代理清除次数。每个模板寄存器保留位，用于存储上一次模板寄存器保持分配值时清除其他模板寄存器的代理清除号。硬件寄存器的内容和每个模板寄存器中的保留位之间的比较确定每个模板寄存器是否应被分配一个清零的值。如果数字不匹配，模板寄存器将分配一个预定的代理清除值。在某些应用中，保留位的数量是固定的，而在其他应用中，可以由设计者或软件来设置保留位数。

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