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1. 外观设计

USD617900S1 End effector tip with undercut bottom jaw 有权
标题翻译：末端效应器尖端与底切下颚
公开(公告)号：USD617900S1
公开(公告)日：2010-06-15
申请号：US29337021
申请日：2009-05-13
申请人： Dylan R. Kingsley , Jeffrey R. Unger , John Twomey , Steven P. Buysse , Pierre Gherardi
设计人： Dylan R. Kingsley , Jeffrey R. Unger , John Twomey , Steven P. Buysse , Pierre Gherardi

2. 外观设计

USD617902S1 End effector tip with undercut top jaw 有权
标题翻译：末端执行器尖端与底切上颌
公开(公告)号：USD617902S1
公开(公告)日：2010-06-15
申请号：US29337023
申请日：2009-05-13
申请人： John Twomey , Jeffrey R. Unger , Dylan R. Kingsley , Steven P. Buysse , Pierre Gherardi
设计人： John Twomey , Jeffrey R. Unger , Dylan R. Kingsley , Steven P. Buysse , Pierre Gherardi

3. 外观设计

USD649643S1 End effector with a rounded tip 有权
标题翻译：末端执行器带圆角
公开(公告)号：USD649643S1
公开(公告)日：2011-11-29
申请号：US29337025
申请日：2009-05-13
申请人： James D. Allen, IV , Jeffrey R. Unger , John Twomey , Jessica E. Olson , Dylan R. Kingsley
设计人： James D. Allen, IV , Jeffrey R. Unger , John Twomey , Jessica E. Olson , Dylan R. Kingsley

4. 外观设计

USD617903S1 End effector pointed tip 有权
标题翻译：末端执行器尖尖
公开(公告)号：USD617903S1
公开(公告)日：2010-06-15
申请号：US29337024
申请日：2009-05-13
申请人： Jeffrey R. Unger , Dylan R. Kingsley , Jessica E. Olson , John Twomey
设计人： Jeffrey R. Unger , Dylan R. Kingsley , Jessica E. Olson , John Twomey

5. 发明申请

US20060095674A1 Tracing instruction flow in an integrated processor 失效
标题翻译：在集成处理器中跟踪指令流程
公开(公告)号：US20060095674A1
公开(公告)日：2006-05-04
申请号：US10925491
申请日：2004-08-25
申请人： John Twomey
发明人： John Twomey
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/30181 , G06F11/364 , G06F12/0888
摘要： Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.
摘要翻译：通过将高速缓存命中降级为高速缓存未命中来跟踪指令流，以允许在总线上使指令提取可见，如果缓存中的指令提取命中，则该指令在总线上不可见。通过使用失败寄存器中的失败命中信号位来控制失败激活，并且其中该位可被编程。

6. 发明授权

US07453305B2 Voltage level shifting circuit, a differential input stage circuit, and a method for providing a level shifted differential signal to a differential input buffer circuit 有权
标题翻译：电压电平移位电路，差分输入级电路以及用于向差分输入缓冲电路提供电平移位差分信号的方法
公开(公告)号：US07453305B2
公开(公告)日：2008-11-18
申请号：US11494168
申请日：2006-07-27
申请人： Brian Anthony Moane , Colm Patrick Ronan , John Twomey
发明人： Brian Anthony Moane , Colm Patrick Ronan , John Twomey
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F2203/45136 , H03F2203/45148 , H03F2203/45151 , H03F2203/45544 , H03F2203/45548 , H03F2203/45576 , H03F2203/45581 , H03F2203/45586
摘要： A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15). First and second high frequency low impedance circuits (22,23) couple the first and second input terminals (10,11) to the first and second output taps (17,19) to provide respective direct current blocked high frequency low impedance paths for the differential signal to first and second differential inputs (7,8) of the differential input buffer circuit (3) for minimizing propagation delays resulting from low pass filters created by the interaction of the first and second resistive voltage divider circuits (16,18) with first and second intrinsic input capacitance (Cb1,Cb2) coupling the first and second differential inputs (7,8) of the differential input buffer circuit (3) to ground.
摘要翻译：用于将差分信号的共模电压移动到差分输入缓冲电路（3）的工作范围内的电压电平移位电路（5）包括：第一电阻分压电路（18），耦合在第一输入端（ 10）和用于接收要参考电平移位差分信号的共模电压的参考电压的电压参考端子（15）以及耦合在第二输入端子（11）之间的第二电阻分压器电路（18））和电压参考端子（15）。差分信号被施加到第一和第二端子（10,11），并且在第一和第二电阻分压器电路（16,18）的第一和第二输出抽头（17,19）上产生电平移位的差分信号，其中电平移位的差分信号的参考模式参考施加到电压参考端子（15）的电压参考。第一和第二高频低阻抗电路（22,23）将第一和第二输入端子（10,11）耦合到第一和第二输出抽头（17,19），以提供相应的直流阻断的高频低阻抗路径，用于差分信号到差分输入缓冲电路（3）的第一和第二差分输入（7,8），用于最小化由第一和第二电阻分压器电路（16,18）与将差分输入缓冲电路（3）的第一和第二差分输入（7,8）耦合到地的第一和第二固有输入电容（C b1，C b2）。

7. 发明授权

US07339941B2 Connecting ethernet based system on a chip integrated circuits in a ring topology 有权
标题翻译：在环形拓扑结构的芯片集成电路上连接基于以太网的系统
公开(公告)号：US07339941B2
公开(公告)日：2008-03-04
申请号：US10778696
申请日：2004-02-13
申请人： John Twomey
发明人： John Twomey
IPC分类号： H04L12/28
CPC分类号： H04L12/4637 , H04L12/42 , H04L45/34
摘要： A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring, and a routing address scheme. Each SOC integrated circuit includes at least one processor, a system bus, a memory controller, at least two Local Area Network (LAN) ports, and a receive channel selection block. The media intercouples the LAN ports of the plurality of SOC integrated circuits to form at least one SOC LAN ring. The routing address scheme serves in routing of data packets on the at least one SOC LAN ring. A routing address of the routing address scheme has a first portion that identifies a source SOC integrated circuit, a second portion that identifies a destination SOC integrated circuit, and a third portion that comprises a LAN address and data.
摘要翻译：多个片上系统（SOC）集成电路，将多个SOC集成电路互连以形成至少一个SOC LAN环的介质和路由地址方案。每个SOC集成电路包括至少一个处理器，系统总线，存储器控制器，至少两个局域网（LAN）端口和接收通道选择块。介质互连多个SOC集成电路的LAN端口以形成至少一个SOC LAN环。所述路由地址方案用于在所述至少一个SOC LAN环上路由数据分组。路由地址方案的路由地址具有识别源SOC集成电路的第一部分，识别目的地SOC集成电路的第二部分和包括LAN地址和数据的第三部分。

8. 发明申请

US20050180437A1 Connecting ethernet based system on a chip integrated circuits in a ring topology 有权
标题翻译：在环形拓扑结构的芯片集成电路上连接基于以太网的系统
公开(公告)号：US20050180437A1
公开(公告)日：2005-08-18
申请号：US10778696
申请日：2004-02-13
申请人： John Twomey
发明人： John Twomey
IPC分类号： H04L12/413 , H04L12/42 , H04L12/46 , H04L12/56 , H04L12/28
CPC分类号： H04L12/4637 , H04L12/42 , H04L45/34
摘要： A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring, and a routing address scheme. Each SOC integrated circuit includes at least one processor, a system bus, a memory controller, at least two Local Area Network (LAN) ports, and a receive channel selection block. The media intercouples the LAN ports of the plurality of SOC integrated circuits to form at least one SOC LAN ring. The routing address scheme serves in routing of data packets on the at least one SOC LAN ring. A routing address of the routing address scheme has a first portion that identifies a source SOC integrated circuit, a second portion that identifies a destination SOC integrated circuit, and a third portion that comprises a LAN address and data.
摘要翻译：多个片上系统（SOC）集成电路，将多个SOC集成电路互连以形成至少一个SOC LAN环的介质和路由地址方案。每个SOC集成电路包括至少一个处理器，系统总线，存储器控制器，至少两个局域网（LAN）端口和接收通道选择块。介质互连多个SOC集成电路的LAN端口以形成至少一个SOC LAN环。所述路由地址方案用于在所述至少一个SOC LAN环上路由数据分组。路由地址方案的路由地址具有识别源SOC集成电路的第一部分，识别目的地SOC集成电路的第二部分和包括LAN地址和数据的第三部分。

9. 发明授权

US07570089B2 Output stage interface circuit for outputting digital data onto a data bus, and a method for operating an output stage interface circuit 有权
标题翻译：用于将数字数据输出到数据总线上的输出级接口电路，以及用于操作输出级接口电路的方法
公开(公告)号：US07570089B2
公开(公告)日：2009-08-04
申请号：US11589020
申请日：2006-10-27
申请人： Colm Patrick Ronan , John Twomey , Brian Anthony Moane , Liam Joseph White
发明人： Colm Patrick Ronan , John Twomey , Brian Anthony Moane , Liam Joseph White
IPC分类号： H03B1/00
CPC分类号： H03K19/00315 , H03K19/003 , H03K19/017518
摘要： An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.
摘要翻译：一种用于与数据总线接口的输出级接口电路，包括用于从电源分别接收高电压和低电压的第一和第二轨道; 数据输出端; 耦合在所述端子和所述第一导轨之间的第一主开关元件，并且包括具有栅极和独立可配置的后栅极的第一主MOS器件，并且响应于施加到所述栅极的第一数据控制信号，所述第一数据控制信号拉动所述数据输出端子上的电压朝向第一轨道电压; 并且响应于所述端子上的电压的第一控制电路被从第一电压基准拉出到第二状态，以将所述后栅极耦合到所述端子，并允许所述MOS器件的栅极与所述端子耦合，当其电压被拉到第二状态时，在端子上呈现高阻抗的第一主MOS器件。

10. 发明申请

US20070260241A1 Open vessel sealing forceps disposable handswitch 有权
标题翻译：开放容器密封钳一次性手动开关
公开(公告)号：US20070260241A1
公开(公告)日：2007-11-08
申请号：US11417375
申请日：2006-05-04
申请人： Casey Dalla Betta , J. Bumgarner , Dylan Kingsley , John Twomey , Brady Walters , David Garrison , Dylan Hushka
发明人： Casey Dalla Betta , J. Bumgarner , Dylan Kingsley , John Twomey , Brady Walters , David Garrison , Dylan Hushka
IPC分类号： A61B18/14
CPC分类号： A61B18/1442 , A61B2017/2945 , A61B2018/0063 , A61B2018/00922 , A61B2018/1432 , A61B2018/1495 , A61B2090/034
摘要： A removable handswitch and electrode assembly for use with a forceps having opposing end effectors and a handle for effecting relative movement of the end effectors with respect to one another includes a housing having at least one portion which removably engages at least a portion of a mechanical forceps and a handswitch assembly disposed on the housing. A pair of electrodes is included which removably engage a distal end of the mechanical forceps such that the electrodes reside in opposing relation to one another. At least one electrode is adapted to connect to an electrosurgical generator through the handswitch assembly. At least one stop member is operatively associated with the electrodes and controls the distance between the opposing electrodes to affect a tissue seal.
摘要翻译：用于具有相对端部执行器的镊子和用于实现端部执行器相对于彼此的相对运动的手柄的可拆卸手动开关和电极组件包括具有至少一个部分的壳体，该至少一个部分可移除地接合机械镊子的至少一部分以及设置在壳体上的手动开关组件。包括一对电极，其可移除地接合机械镊子的远端，使得电极彼此相对地存在。至少一个电极适于通过手动开关组件连接到电外科发生器。至少一个止动构件与电极可操作地相关联并且控制相对电极之间的距离以影响组织密封。

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