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1. 发明公开

CN102158216A 接收电路无效
公开(公告)号：CN102158216A
公开(公告)日：2011-08-17
申请号：CN201110008085.4
申请日：2011-01-12
申请人：瑞萨电子株式会社
发明人：中村涉
IPC分类号： H03K19/0175
CPC分类号： H03F3/45475 , H03F1/0266 , H03F3/45959 , H03F2200/27 , H03F2200/282 , H03F2200/294 , H03F2200/451 , H03F2200/471 , H03F2203/45418 , H03F2203/45424 , H03F2203/45434 , H03F2203/45541 , H03F2203/45578 , H03F2203/45581 , H03F2203/45588 , H03F2203/45594 , H03F2203/45596
摘要：本发明提供一种接收电路。根据本发明的示例性方面的接收电路包括：第一分压电路，该第一分压电路基于第一和第二电阻器之间的电阻比率来输出通过差分信号中的一个的分压而获得的第一输入信号；第二分压电路，该第二分压电路基于第三和第四电阻器的电阻比率来输出通过差分信号的另一个的分压而获得的第二输入信号；差分放大器，该差分放大器放大第一和第二输入信号之间的差分分量；共模电压检测电路，该共模电压检测电路检测差分信号的共模电压；以及偏置电压切换电路，该偏置电压切换电路基于共模电压来切换偏置电压的电压值。

2. 发明公开

CN102356545A 使用巨磁阻传感器的放大驱动单元以及使用其的诊断装置无效转让
公开(公告)号：CN102356545A
公开(公告)日：2012-02-15
申请号：CN201080012572.1
申请日：2010-03-19
申请人： LG伊诺特有限公司
发明人：金英默 , 金廷律 , 崔万休 , 李忠完 , 梁智惠 , 姜文淑
IPC分类号： H03F3/45 , A61B5/05
CPC分类号： A61B5/055 , G01R33/093 , H01F10/325 , H03F3/347 , H03F3/45475 , H03F3/45928 , H03F3/45991 , H03F2200/261 , H03F2203/45101 , H03F2203/45152 , H03F2203/45154 , H03F2203/45581 , H03F2203/45596
摘要：本发明涉及一种放大单元，其包括：上拉下拉单元，对GMR传感器所提供的正GMR信号和负GMR信号进行上拉或下拉；GMR放大单元，包括多个放大单元，该多个放大单元根据所述GMR传感器对所述独立型信号和负GMR信号之差进行放大从而产生所述GMR信号；低通滤波器，使所述GMR信号中的噪声衰减；参考转换单元，产生用于产生GMR信号的具有预定范围的参考电压；以及增益转换单元，将输入所述多个放大单元中的所述GMR信号放大几十或上百倍。

3. 发明申请

US20090201086A1 Current sense amplifier with extended common mode voltage range 有权
标题翻译：具有扩展共模电压范围的电流检测放大器
公开(公告)号：US20090201086A1
公开(公告)日：2009-08-13
申请号：US12069967
申请日：2008-02-13
申请人： Willem Johannes Kindt , Michiel Antonius Petrus Pertijs
发明人： Willem Johannes Kindt , Michiel Antonius Petrus Pertijs
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/34 , H03F3/245 , H03F3/45103 , H03F2203/45581 , H03F2203/45586 , H03F2203/45588
摘要： A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit.
摘要翻译：电路包括输入级，其被配置为接收和放大输入信号以产生放大信号，其中输入信号参考较高电压并与共模电压相关联。电路还包括电平移位器电阻器，其被配置为对放大的信号进行电平移位以产生移位的信号。电平移位器电阻被配置为提供电压降，使得移位的信号参考较低的电压。输入级可以包括漂浮在衬底的一个或多个隔离部分中的多个晶体管，其中晶体管在输入级中执行放大。电路还可以包括被配置为控制通过电平移位器电阻器的电流的电路，使得电压降取决于输入信号的共模电压。此外，较低的电压可能在电路的电源轨之间。

4. 发明申请

US20070069816A1 Method for transconductance linearization for DC-coupled applications 有权
标题翻译：直流耦合应用的跨导线性化方法
公开(公告)号：US20070069816A1
公开(公告)日：2007-03-29
申请号：US11599247
申请日：2006-11-14
申请人： Arya Behzad
发明人： Arya Behzad
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F1/26 , H03F3/45183 , H03F2200/294 , H03F2200/372 , H03F2203/45288 , H03F2203/45541 , H03F2203/45564 , H03F2203/45581 , H03F2203/45594
摘要： A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the first transconductance stage becomes active before the second transconductance stage with respect to the magnitude of a differential input voltage, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current converter. As each of the plurality of transconductance stages is biased differently from the others, the various transconductance stages are biased on to differing amounts based upon the biasing signals as well as the input signal.
摘要翻译： AB类电压 - 电流转换器包括产生线性化输出和偏置电路的多个DC耦合跨导级。偏置电路产生大于产生的次级偏置电压的初级偏置电压。因此，第一跨导级相对于差分输入电压的幅度在第二跨导级之前变为有效，从而允许从初级级的跨导添加（或减去）次级跨导级的跨导，以改善 AB类电压 - 电流转换器的整体跨导。由于多个跨导级中的每一个与其它跨导级的偏置不同，所以基于偏置信号以及输入信号将各种跨导级偏置到不同的量。

5. 发明公开

EP1852972A1 Single-ended to differential buffer amplifier 审中-公开
标题翻译： Eintakt- zu GegentaktPufferverstärker
公开(公告)号：EP1852972A1
公开(公告)日：2007-11-07
申请号：EP06009071.9
申请日：2006-05-02
申请人： Infineon Technologies AG
发明人： Grewing, Christian , Einerman, Wenche
IPC分类号： H03F3/343
CPC分类号： H03F3/45179 , H03F3/347 , H03F3/45273 , H03F3/45636 , H03F2203/45542 , H03F2203/45548 , H03F2203/45581 , H03F2203/45588 , H03F2203/45674
摘要： The invention relates to an input buffer amplifier 1 suitable for a system on chip device. The input buffer amplifier 1 comprises a single ended input and a differential output. The input terminal is connected to a first differential stage 2 comprising two transistors T 1 , T 2 and to a second differential stage 3 comprising two transistors T 3 , T 4 . The first and second differential stages 2, 3 are further connected to a first and second load, for example current mirrors 10, 20, being connected so as to provide a differential output at the output terminals OUT P , OUT N .
摘要翻译：本发明涉及一种适用于片上系统的输入缓冲放大器1。输入缓冲放大器1包括单端输入和差分输出。输入端子连接到包括两个晶体管T 1，T 2的第一差分级2和包括两个晶体管T 3，T 4的第二差分级3。第一差分级和第二差分级2,3进一步连接到第一和第二负载，例如电流镜10,20，以便在输出端OUT，OUT N处提供差分输出。

6. 发明公开

EP2409402A2 AMPLIFYING DRIVING UNIT USING GIANT MAGNETO RESISTANCE SENSOR AND DIAGNOSIS DEVICE USING THE SAME 审中-公开
标题翻译：采用巨磁阻抗传感器和诊断装置的放大驱动装置
公开(公告)号：EP2409402A2
公开(公告)日：2012-01-25
申请号：EP10753723.5
申请日：2010-03-19
申请人： LG Innotek Co., Ltd.
发明人： KIM, Young Muk , KIM, Jeong Ryul , CHOI, Man Hue , LEE, Chung Wan , YANG, Ji Hye , KANG, Mun Suk
IPC分类号： H03F3/45 , A61B5/05
CPC分类号： A61B5/055 , G01R33/093 , H01F10/325 , H03F3/347 , H03F3/45475 , H03F3/45928 , H03F3/45991 , H03F2200/261 , H03F2203/45101 , H03F2203/45152 , H03F2203/45154 , H03F2203/45581 , H03F2203/45596
摘要： The present invention relates to an amplifying unit comprising: a pull up down unit pulling up or pulling down a positive GMR signal and a negative GMR signal provide by a GMR sensor; a GMR amplifying unit including a plurality of amplifying units generating a GMR signal by amplifying a difference between the stand-alone type signal and the negative GMR signal according to the GMR sensor; a low pass filtering unit attenuating noise of the GMR signal; a reference converting unit generating a reference voltage having a predetermined range for generating a GMR signal; and a gain converting unit amplifying the GMR signals inputted to the plurality of amplifying units by several ten or hundred times.
摘要翻译：本发明涉及一种放大单元，包括：上拉单元，上拉或下拉由GMR传感器提供的正GMR信号和负GMR信号; GMR放大单元，其包括多个放大单元，所述多个放大单元通过根据所述GMR传感器放大所述独立型信号与所述负GMR信号之间的差来生成GMR信号; 低通滤波单元，衰减GMR信号的噪声; 参考转换单元，产生具有用于产生GMR信号的预定范围的参考电压; 以及增益转换单元，将输入到所述多个放大单元的GMR信号放大数十倍或数百倍。

7. 发明申请

US20110169565A1 Receiving circuit 有权
标题翻译：接收电路
公开(公告)号：US20110169565A1
公开(公告)日：2011-07-14
申请号：US12929290
申请日：2011-01-12
申请人： Wataru Nakamura
发明人： Wataru Nakamura
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/0266 , H03F3/45959 , H03F2200/27 , H03F2200/282 , H03F2200/294 , H03F2200/451 , H03F2200/471 , H03F2203/45418 , H03F2203/45424 , H03F2203/45434 , H03F2203/45541 , H03F2203/45578 , H03F2203/45581 , H03F2203/45588 , H03F2203/45594 , H03F2203/45596
摘要： A receiving circuit in accordance with an exemplary aspect of the present invention includes a first voltage-dividing circuit that outputs a first input signal obtained by voltage division of one of differential signals based on the resistance ratio between first and second resistors, a second voltage-dividing circuit that outputs a second input signal obtained by voltage division of the other of the differential signals based on the resistance ratio between third and fourth resistors, a differential amplifier that amplifies the differential component between the first and second input signals, a common-mode voltage detection circuit that detects the common-mode voltage of the differential signals, and a bias voltage switching circuit that switches the voltage value of a bias voltage based on the common-mode voltage.
摘要翻译：根据本发明的示例性方面的接收电路包括：第一分压电路，其输出基于第一和第二电阻器之间的电阻比的差分信号中的一个分压获得的第一输入信号;第二电压 - 分压电路，输出基于第三和第四电阻器之间的电阻比对另一个差分信号进行分压而获得的第二输入信号;放大第一和第二输入信号之间的差分分量的差分放大器;共模电压检测电路，其检测所述差分信号的共模电压;以及偏置电压切换电路，其基于所述共模电压来切换偏置电压的电压值。

8. 发明授权

US07453305B2 Voltage level shifting circuit, a differential input stage circuit, and a method for providing a level shifted differential signal to a differential input buffer circuit 有权
标题翻译：电压电平移位电路，差分输入级电路以及用于向差分输入缓冲电路提供电平移位差分信号的方法
公开(公告)号：US07453305B2
公开(公告)日：2008-11-18
申请号：US11494168
申请日：2006-07-27
申请人： Brian Anthony Moane , Colm Patrick Ronan , John Twomey
发明人： Brian Anthony Moane , Colm Patrick Ronan , John Twomey
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F2203/45136 , H03F2203/45148 , H03F2203/45151 , H03F2203/45544 , H03F2203/45548 , H03F2203/45576 , H03F2203/45581 , H03F2203/45586
摘要： A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15). First and second high frequency low impedance circuits (22,23) couple the first and second input terminals (10,11) to the first and second output taps (17,19) to provide respective direct current blocked high frequency low impedance paths for the differential signal to first and second differential inputs (7,8) of the differential input buffer circuit (3) for minimizing propagation delays resulting from low pass filters created by the interaction of the first and second resistive voltage divider circuits (16,18) with first and second intrinsic input capacitance (Cb1,Cb2) coupling the first and second differential inputs (7,8) of the differential input buffer circuit (3) to ground.
摘要翻译：用于将差分信号的共模电压移动到差分输入缓冲电路（3）的工作范围内的电压电平移位电路（5）包括：第一电阻分压电路（18），耦合在第一输入端（ 10）和用于接收要参考电平移位差分信号的共模电压的参考电压的电压参考端子（15）以及耦合在第二输入端子（11）之间的第二电阻分压器电路（18））和电压参考端子（15）。差分信号被施加到第一和第二端子（10,11），并且在第一和第二电阻分压器电路（16,18）的第一和第二输出抽头（17,19）上产生电平移位的差分信号，其中电平移位的差分信号的参考模式参考施加到电压参考端子（15）的电压参考。第一和第二高频低阻抗电路（22,23）将第一和第二输入端子（10,11）耦合到第一和第二输出抽头（17,19），以提供相应的直流阻断的高频低阻抗路径，用于差分信号到差分输入缓冲电路（3）的第一和第二差分输入（7,8），用于最小化由第一和第二电阻分压器电路（16,18）与将差分输入缓冲电路（3）的第一和第二差分输入（7,8）耦合到地的第一和第二固有输入电容（C b1，C b2）。

9. 发明授权

US07449896B2 Current sensor using level shift circuit 有权
标题翻译：电流传感器使用电平移位电路
公开(公告)号：US07449896B2
公开(公告)日：2008-11-11
申请号：US11496981
申请日：2006-07-31
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： G01R27/08
CPC分类号： H03F3/45475 , G01R19/0092 , H03F3/345 , H03F2200/261 , H03F2200/462 , H03F2203/45581
摘要： A circuit for sensing a current includes a first upper resistor having a first end coupled to a first end of a sense resistor, the sense resistor being configured to receive an input current. A second upper resistor has a first end coupled to a second end of the sense resistor, so that the sense resistor defines a first potential between the first and second ends of the sense resistor. A first lower resistor is provided between the first upper resistor and the ground. A second lower resistor is provided between the second upper resistor and the ground. An amplifier has a first input node and a second input node, the first input node being coupled to a node between the first upper resistor and the first lower resistor. The second input node is coupled to a node between the to the second upper resistor and the second lower resistor. The first and second input nodes defines a second potential corresponding to the first potential.
摘要翻译：用于感测电流的电路包括具有耦合到检测电阻器的第一端的第一端的第一上电阻器，感测电阻器被配置为接收输入电流。第二上电阻器具有耦合到检测电阻器的第二端的第一端，使得检测电阻器在感测电阻器的第一端和第二端之间限定第一电位。在第一上电阻器和地之间提供第一下电阻器。在第二上电阻器和地之间提供第二下电阻器。放大器具有第一输入节点和第二输入节点，第一输入节点耦合到第一上电阻器和第一下电阻器之间的节点。第二输入节点耦合到第二上电阻器和第二下电阻器之间的节点。第一和第二输入节点定义对应于第一电位的第二电位。

10. 发明授权

US07254164B2 Method for transconductance linearization for DC-coupled applications 有权
公开(公告)号：US07254164B2
公开(公告)日：2007-08-07
申请号：US11599247
申请日：2006-11-14
申请人： Arya Reza Behzad
发明人： Arya Reza Behzad
IPC分类号： H04B1/38
CPC分类号： H03F1/3211 , H03F1/26 , H03F3/45183 , H03F2200/294 , H03F2200/372 , H03F2203/45288 , H03F2203/45541 , H03F2203/45564 , H03F2203/45581 , H03F2203/45594
摘要： A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the first transconductance stage becomes active before the second transconductance stage with respect to the magnitude of a differential input voltage, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current converter. As each of the plurality of transconductance stages is biased differently from the others, the various transconductance stages are biased on to differing amounts based upon the biasing signals as well as the input signal.

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