会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Galvanically isolated charge balance system
    • 电隔离电荷平衡系统
    • US07612537B2
    • 2009-11-03
    • US11657824
    • 2007-01-25
    • John WynneEamon Hynes
    • John WynneEamon Hynes
    • H02J7/00
    • H02J7/0016H02J7/0021
    • A galvanically isolated charge balance system for a multicell battery includes a balancing circuit associated with each cell; each balancing circuit including a flying capacitor; a variable conductance switch; and a biasing circuit for the variable conductance switch; and a galvanically isolating MEMS switching device for selectively connecting the flying capacitor to a voltage supply to charge it to a predetermined voltage and to the biasing circuit for setting the variable conductance switch to adjust the charge on its associated cell to a preselected level.
    • 用于多电池电池的电隔离电荷平衡系统包括与每个电池相关联的平衡电路; 每个平衡电路包括一个飞行电容器; 可变电导开关; 以及用于可变电导开关的偏置电路; 以及用于选择性地将飞秒电容器连接到电压源以将其充电至预定电压的电气隔离MEMS开关装置,以及用于设置可变电导开关以将其相关联的电池上的电荷调节到预选电平的偏置电路。
    • 9. 发明授权
    • Method of invoking a power-down mode on an integrated circuit by
monitoring a normally changing input signal
    • 通过监视正常变化的输入信号在集成电路上调用掉电模式的方法
    • US6147528A
    • 2000-11-14
    • US41937
    • 1998-03-13
    • John O'DowdJohn Wynne
    • John O'DowdJohn Wynne
    • G06F1/24G06F1/32H03L7/00
    • G06F1/3287G06F1/24G06F1/3203Y02B60/1282
    • An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.
    • 集成电路包括响应于集成电路的输入处的正常变化的信号以实现电路的主要功能的装置,以及用于在集成电路的问题的输入端监视该正常变化的信号的装置。 该监视装置响应于暂停正常变化的信号以传送信号以实现电路的次要功能。 在示例性实施例中,本发明旨在实现电路的掉电,而不使用明确的掉电或复位引脚。 通常以最小速率变化的输入信号,例如, 优选地,时钟信号被保持在固定状态一个最小持续时间以调用复位或掉电模式。 因此,集成电路可以在没有明显的掉电或复位引脚可用的情况下掉电或复位。
    • 10. 发明授权
    • Low distortion CMOS switch system
    • 低失真CMOS开关系统
    • US5422588A
    • 1995-06-06
    • US76456
    • 1993-06-14
    • John Wynne
    • John Wynne
    • H03K17/14H03K17/687
    • H03K17/145H03K17/6872
    • A low distortion CMOS switch system includes a plurality of N-channel and a plurality of P-channel transistors with their drain and source terminals connected in parallel for receiving an input signal to be switched; and a control circuit for providing a different positive drive voltage to the gate of each of the N-channel transistors and a different negative drive voltage to the gate of each of the P-channel transistors to produce substantially constant "on" resistance, R.sub.ON, throughout the range of the switched signal conducted through the drain and source terminals, and for providing the same negative drive voltage to the gate of each of the N channel transistors and the same positive drive voltage to the gate of each of the P channel transistors to turn off the transistors.
    • 低失真CMOS开关系统包括多个N沟道和多个P沟道晶体管,其漏极和源极端子并联连接以接收要切换的输入信号; 以及控制电路,用于向每个N沟道晶体管的栅极提供不同的正驱动电压,并向每个P沟道晶体管的栅极提供不同的负驱动电压,以产生基本恒定的“导通”电阻RON, 在通过漏极和源极端子传导的开关信号的整个范围内,并且向N沟道晶体管中的每一个的栅极提供相同的负驱动电压,以及向每个P沟道晶体管的栅极提供相同的正驱动电压, 关闭晶体管。