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1. 发明申请

US20110231691A1 Synchronization in data processing layers 有权
标题翻译：数据处理层同步
公开(公告)号：US20110231691A1
公开(公告)日：2011-09-22
申请号：US12659668
申请日：2010-03-16
申请人： John Michael Horley , Nebojsa Makljenovic , Katherine Elizabeth Kneebone , Michael John Williams , Ian William Spray
发明人： John Michael Horley , Nebojsa Makljenovic , Katherine Elizabeth Kneebone , Michael John Williams , Ian William Spray
IPC分类号： G06F9/00
CPC分类号： G06F9/545 , G06F11/3632 , G06F11/3636 , G06F11/3656
摘要： A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.
摘要翻译：提供一种数据处理装置，其具有包括至少两个数据处理层的层的层级，每个数据处理层被配置为接收数据并且生成经处理的数据，以根据该特定于该层级的协议生成用于传递到所述层级中的下一个较低层数据处理层。每个数据处理层被间歇地配置以将同步信息添加到其处理的数据，同步信息提供解释处理的数据所需的语义信息。每个数据处理层还被配置为响应于从所述层级中的较低层接收到的同步请求信号而输出其同步信息，并且当输出其同步信息时，配置至少一个数据处理层以发出其同步请求信号到层次结构中的较高层。

2. 发明授权

US09965342B2 Synchronization in data processing layers 有权
公开(公告)号：US09965342B2
公开(公告)日：2018-05-08
申请号：US12659668
申请日：2010-03-16
申请人： John Michael Horley , Nebojsa Makljenovic , Katherine Elizabeth Kneebone , Michael John Williams , Ian William Spray
发明人： John Michael Horley , Nebojsa Makljenovic , Katherine Elizabeth Kneebone , Michael John Williams , Ian William Spray
IPC分类号： G06F9/00 , G06F9/54 , G06F13/42 , G06F11/36
CPC分类号： G06F9/545 , G06F11/3632 , G06F11/3636 , G06F11/3656
摘要： A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.

3. 发明申请

US20110202801A1 Trace data priority selection 有权
标题翻译：跟踪数据优先级选择
公开(公告)号：US20110202801A1
公开(公告)日：2011-08-18
申请号：US12929744
申请日：2011-02-14
申请人： John Michael Horley , Michael John Williams , Katherine Elizabeth Kneebone , Alastair David Reid
发明人： John Michael Horley , Michael John Williams , Katherine Elizabeth Kneebone , Alastair David Reid
IPC分类号： G06F11/34
CPC分类号： G06F11/348
摘要： An integrated circuit 2 is provided with a data source 6 in the form of a processor executing program instructions connected via a bus interconnect 16 to a trace output device 8. The trace output device 8 is memory mapped. Different memory addresses that are mapped to the trace output device 8 are associated with different priority levels. Trace data written to at least one memory address has a first level of priority in which it is either accepted or the transfer is stalled until the data can be processed by the trace output device 8. Another level of priority associated with a different memory address is such that the data is always accepted but is discarded if the trace output device 8 does not have the ability to process, e.g. store that data at that time.
摘要翻译：集成电路2设置有处理器形式的数据源6，该处理器执行通过总线互连16连接到跟踪输出设备8的程序指令。跟踪输出设备8被存储器映射。映射到跟踪输出设备8的不同的存储器地址与不同的优先级相关联。写入至少一个存储器地址的跟踪数据具有第一级别的优先级，其中它被接受或者传输被停止，直到数据可以被跟踪输出设备8处理。与不同的存储器地址相关联的另一级别的优先级是使得数据总是被接受，但是如果跟踪输出设备8不具有处理能力，则被丢弃存储当时的数据。

4. 发明授权

US08887001B2 Trace data priority selection 有权
标题翻译：跟踪数据优先级选择
公开(公告)号：US08887001B2
公开(公告)日：2014-11-11
申请号：US12929744
申请日：2011-02-14
申请人： John Michael Horley , Michael John Williams , Katherine Elizabeth Kneebone , Alastair David Reid
发明人： John Michael Horley , Michael John Williams , Katherine Elizabeth Kneebone , Alastair David Reid
IPC分类号： G06F11/00 , G06F11/34
CPC分类号： G06F11/348
摘要： An integrated circuit 2 is provided with a data source 6 in the form of a processor executing program instructions connected via a bus interconnect 16 to a trace output device 8. The trace output device 8 is memory mapped. Different memory addresses that are mapped to the trace output device 8 are associated with different priority levels. Trace data written to at least one memory address has a first level of priority in which it is either accepted or the transfer is stalled until the data can be processed by the trace output device 8. Another level of priority associated with a different memory address is such that the data is always accepted but is discarded if the trace output device 8 does not have the ability to process, e.g. store that data at that time.
摘要翻译：集成电路2设置有处理器形式的数据源6，该处理器执行通过总线互连16连接到跟踪输出设备8的程序指令。跟踪输出设备8被存储器映射。映射到跟踪输出设备8的不同的存储器地址与不同的优先级相关联。写入至少一个存储器地址的跟踪数据具有第一级别的优先级，其中它被接受或者传输被停止，直到数据可以被跟踪输出设备8处理。与不同的存储器地址相关联的另一级别的优先级是使得数据总是被接受，但是如果跟踪输出设备8不具有处理能力，则被丢弃存储当时的数据。

5. 发明申请

US20080098262A1 Performing diagnostic operations upon an asymmetric multiprocessor apparatus 有权
标题翻译：对非对称多处理器设备执行诊断操作
公开(公告)号：US20080098262A1
公开(公告)日：2008-04-24
申请号：US11907881
申请日：2007-10-18
申请人： Simon Andrew Ford , Alastair David Reid , Katherine Elizabeth Kneebone , Edmund Grimley-Evans
发明人： Simon Andrew Ford , Alastair David Reid , Katherine Elizabeth Kneebone , Edmund Grimley-Evans
IPC分类号： G06F11/28
CPC分类号： G06F11/362 , G06F11/3636
摘要： An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10. A master diagnostic unit 26 tracks the migration of thread execution between the different execution mechanisms 6, 8, 10 so that the execution of a given thread can be followed by the diagnostic mechanisms 20, 22, 24, 26 and this information provided to the programmer. The execution mechanisms 6, 8, 10 can be diverse such as a general purpose processor 6, a DMA unit 12, a coprocessor, an VLIW processor, a digital signal processor 8 and a hardware accelerator 10. The asymmetric multiprocessor apparatus 2 will also typically include an asymmetric memory hierarchy such as including two or more of a global memory, a shared memory 16, a private memory 18 and a cache memory 14.
摘要翻译：提供了非对称多处理器装置2，其中相应的从属诊断单元20,22,24与相应的执行机构6,8,10相关联。主诊断单元26跟踪不同执行机构6,8,10之间的线程执行的迁移，使得给定线程的执行可以跟随诊断机构20,22,24,26，并且提供给程序员的信息。执行机构6,8,10可以是多样的，例如通用处理器6，DMA单元12，协处理器，VLIW处理器，数字信号处理器8和硬件加速器10。非对称多处理器装置2还通常将包括非对称存储器层级，例如包括全局存储器，共享存储器16，专用存储器18和高速缓存存储器14中的两个或更多个。

6. 发明申请

US20080098207A1 Analyzing diagnostic data generated by multiple threads within an instruction stream 审中-公开
标题翻译：分析指令流中多个线程生成的诊断数据
公开(公告)号：US20080098207A1
公开(公告)日：2008-04-24
申请号：US11898363
申请日：2007-09-11
申请人： Alastair David Reid , Simon Andrew Ford , Katherine Elizabeth Kneebone
发明人： Alastair David Reid , Simon Andrew Ford , Katherine Elizabeth Kneebone
IPC分类号： G06F9/44
CPC分类号： G06F11/362 , G06F11/3636
摘要： A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering data, said reordering data comprising data relating to said computer program; and (iii) outputting said reordered diagnostic data. In general, the instructions streams are processed by a plurality of processing units arranged to process at least some of said instructions in parallel, said diagnostic data being received from said plurality of processing units.
摘要翻译：一种用于输出与源自计算机程序的指令流的处理有关的诊断数据的诊断方法，其中包括多个线程的至少一些所述指令流被公开。该方法包括以下步骤：（i）接收诊断数据; （ii）根据重新排序数据对所接收的诊断数据重新排序，所述重排序数据包括与所述计算机程序有关的数据; 和（iii）输出所述重新排序的诊断数据。通常，指令流由多个处理单元处理，多个处理单元被布置为并行处理至少一些所述指令，所述诊断数据从所述多个处理单元接收。

7. 发明授权

US07809989B2 Performing diagnostic operations upon an asymmetric multiprocessor apparatus 有权
标题翻译：对非对称多处理器设备执行诊断操作
公开(公告)号：US07809989B2
公开(公告)日：2010-10-05
申请号：US11907881
申请日：2007-10-18
申请人： Simon Andrew Ford , Alastair David Reid , Katherine Elizabeth Kneebone , Edmund Grimley-Evans
发明人： Simon Andrew Ford , Alastair David Reid , Katherine Elizabeth Kneebone , Edmund Grimley-Evans
IPC分类号： G06F11/00
CPC分类号： G06F11/362 , G06F11/3636
摘要： An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10. A master diagnostic unit 26 tracks the migration of thread execution between the different execution mechanisms 6, 8, 10 so that the execution of a given thread can be followed by the diagnostic mechanisms 20, 22, 24, 26 and this information provided to the programmer. The execution mechanisms 6, 8, 10 can be diverse such as a general purpose processor 6, a DMA unit 12, a coprocessor, an VLIW processor, a digital signal processor 8 and a hardware accelerator 10. The asymmetric multiprocessor apparatus 2 will also typically include an asymmetric memory hierarchy such as including two or more of a global memory, a shared memory 16, a private memory 18 and a cache memory 14.
摘要翻译：提供了非对称多处理器装置2，其中相应的从诊断单元20,22,24与相应的执行机构6,8,10相关联。主诊断单元26跟踪不同执行机构6,8,10之间的线程执行的迁移。 10，使得给定线程的执行可以跟随诊断机构20,22,24,26，并且该信息被提供给程序员。执行机构6,8,10可以是多样的，例如通用处理器6，DMA单元12，协处理器，VLIW处理器，数字信号处理器8和硬件加速器10.非对称多处理器装置2也将典型地包括诸如包括全局存储器，共享存储器16，专用存储器18和高速缓冲存储器14中的两个或更多个的非对称存储器层级。

8. 发明申请

US20090019256A1 Memory transaction handling in a data processing apparatus 审中-公开
标题翻译：数据处理装置中的存储器事务处理
公开(公告)号：US20090019256A1
公开(公告)日：2009-01-15
申请号：US12213147
申请日：2008-06-16
申请人： Katherine Elizabeth Kneebone , David Hennah Mansell
发明人： Katherine Elizabeth Kneebone , David Hennah Mansell
IPC分类号： G06F12/06
CPC分类号： G06F12/10
摘要： A data processing apparatus is provided comprising a memory, memory management unit and identification circuitry for identifying a predetermined type of data access transaction within a plurality of received data access transactions. The memory management unit is responsive to the predetermined type of data access transaction to both permit completion of a data access and to cause an exception to be raised despite completion of the data access having been permitted.
摘要翻译：提供了一种数据处理装置，包括存储器，存储器管理单元和识别电路，用于在多个接收的数据访问事务中识别预定类型的数据访问事务。存储器管理单元响应于预定类型的数据访问事务，以允许完成数据访问，并且在数据访问已被允许完成时引起异常。

9. 发明申请

US20080133897A1 Diagnostic apparatus and method 审中-公开
标题翻译：诊断仪和方法
公开(公告)号：US20080133897A1
公开(公告)日：2008-06-05
申请号：US11907112
申请日：2007-10-09
申请人： Alastair David Reid , Simon Andrew Ford , Katherine Elizabeth Kneebone
发明人： Alastair David Reid , Simon Andrew Ford , Katherine Elizabeth Kneebone
IPC分类号： G06F9/30
CPC分类号： G06F11/3632 , G06F11/362 , G06F11/3636
摘要： A diagnostic method is described for generating diagnostic data relating to processing of an instruction stream, wherein said instruction stream has been compiled from a source instruction stream to include multiple threads, said method comprising the steps of: (i) initiating a diagnostic procedure in which at least a portion of said instruction stream is executed; (ii) controlling a scheduling order for executing instructions within said at least a portion of said instruction stream to cause execution of a sequence of thread portions, said sequence being determined in response to one or more rules, at least one of said rules defining an order of execution of said thread portions to follow an order of said source instruction stream. In this way, the diagnostic method can generate a debug view of a parallelised program which is the same as, or at least similar to, a debug view which would be provided when debugging the original non-parallelised program.
摘要翻译：描述了一种用于产生与指令流的处理有关的诊断数据的诊断方法，其中所述指令流已经从源指令流被编译以包括多个线程，所述方法包括以下步骤：（i）启动诊断过程，其中执行所述指令流的至少一部分; （ii）控制用于执行在所述指令流的所述至少一部分内的指令的调度顺序以引起线程部分序列的执行，所述序列响应于一个或多个规则来确定，所述规则中的至少一个限定所述线程部分的执行顺序遵循所述源指令流的顺序。以这种方式，诊断方法可以生成与调试原始非并行化程序时将提供的调试视图相同或至少相似的并行程序的调试视图。

10. 发明授权

US09858169B2 Monitoring a data processing apparatus and summarising the monitoring data 有权
公开(公告)号：US09858169B2
公开(公告)日：2018-01-02
申请号：US12458287
申请日：2009-07-07
申请人： Alastair David Reid , Katherine Elizabeth Kneebone , Jan Guffens , Lee Douglas Smith
发明人： Alastair David Reid , Katherine Elizabeth Kneebone , Jan Guffens , Lee Douglas Smith
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F11/3471 , G06F2201/86 , G06F2201/88
摘要： A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.

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