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1. 发明授权

US06870901B1 Design and architecture of an impairment diagnosis system for use in communications systems 失效
标题翻译：用于通信系统的损伤诊断系统的设计和架构
公开(公告)号：US06870901B1
公开(公告)日：2005-03-22
申请号：US09711684
申请日：2000-11-10
申请人： Thorkell Gudmundsson , John Josef Hench , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Harbinder Singh , Yaolong Tan , Sunil C. Shah
发明人： Thorkell Gudmundsson , John Josef Hench , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Harbinder Singh , Yaolong Tan , Sunil C. Shah
IPC分类号： H04B3/32 , H04L1/24 , H04L12/24 , H04L25/02 , H04L25/03 , H04L27/26 , H04M3/24 , H04M3/30 , H04M3/36 , H05M1/24 , H04L12/42
CPC分类号： H04L41/046 , H04B3/32 , H04L1/24 , H04L25/0204 , H04L25/03305 , H04L27/2608 , H04L41/0631 , H04L41/142 , H04L41/145 , H04L2025/03414 , H04M3/247 , H04M3/306 , H04M3/36
摘要： A method and apparatus are disclosed. The method includes one or more of the following: compiling statistical models of physical layers of a communications system; creating a priori distributions of cross-talk transfer functions; storing the models and the a priori distribution in a storage medium; and using the models and the a priori distributions to diagnose probable causes of events detected in said communications system.
摘要翻译：公开了一种方法和装置。该方法包括以下一个或多个：编译通信系统的物理层的统计模型; 创建串扰传递函数的先验分布; 将模型和先验分布存储在存储介质中; 以及使用所述模型和先验分布来诊断在所述通信系统中检测到的事件的可能原因。

2. 发明授权

US07864692B1 Method and apparatus for the prediction and optimization in impaired communication systems 有权
标题翻译：用于通信系统受损的预测和优化的方法和装置
公开(公告)号：US07864692B1
公开(公告)日：2011-01-04
申请号：US09710487
申请日：2000-11-10
申请人： John Josef Hench , Thorkell Gudmundsson , Ioannis Kanellakopoulos , Sunil C. Shah , Gurcan Aral , Yaolong Tan
发明人： John Josef Hench , Thorkell Gudmundsson , Ioannis Kanellakopoulos , Sunil C. Shah , Gurcan Aral , Yaolong Tan
IPC分类号： H04L12/26
CPC分类号： H04L41/046 , H04B3/32 , H04B3/487 , H04L1/20 , H04L25/0204 , H04L25/03305 , H04L27/2608 , H04L41/06 , H04L41/147 , H04L43/00 , H04L43/0811 , H04L43/50 , H04L2025/03414 , H04M3/2209 , H04M3/244 , H04M3/30 , H04M3/303 , H04Q3/0087
摘要： A method and apparatus are disclosed for the prediction and optimization of a communications system. The present invention provides for the prediction and optimization of the performance of a communications system comprising the steps of inputting a plurality of channels, predicting a performance of each channel using a plurality of parameters to characterize the performance of the channel, and possibly optimizing the parameters of each channel according to a design criteria.
摘要翻译：公开了一种用于预测和优化通信系统的方法和装置。本发明提供了对通信系统的性能的预测和优化，包括以下步骤：输入多个信道，使用多个参数来预测每个信道的性能以表征信道的性能，并且可能优化参数根据设计标准。

3. 发明授权

US06970560B1 Method and apparatus for impairment diagnosis in communication systems 失效
标题翻译：通信系统中损伤诊断的方法和装置
公开(公告)号：US06970560B1
公开(公告)日：2005-11-29
申请号：US09710703
申请日：2000-11-10
申请人： John Josef Hench , Thorkell Gudmundsson , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Yaolong Tan , Harbinder Singh , Sunil C. Shah
发明人： John Josef Hench , Thorkell Gudmundsson , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Yaolong Tan , Harbinder Singh , Sunil C. Shah
IPC分类号： H04B3/46 , H04M1/76 , H04M3/08 , H04M3/18 , H04M3/30
CPC分类号： H04M3/085 , H04B3/487 , H04L5/0007 , H04L5/0046 , H04M3/18 , H04M3/304
摘要： Events that occur in a number of in domain communication channels where each channel is used by a communication service, are detected. A Bayesian Belief Network (BBN) defines a probabilistic cause-effect relationship between each cause and each effect on a victim channel. The probability of each of a number of possible causes as being a cause of interference in the victim channel is determined, by propagating observations of the interference backwards through the BBN.
摘要翻译：检测到在通信服务使用每个信道的域通信信道中的多个中发生的事件。贝叶斯信仰网络（BBN）定义了每个原因与每个对受害者信道的影响之间的概率因果关系。通过BBN向后传播干扰的观测来确定多个可能原因中的每一个作为受害信道干扰的原因的概率。

4. 发明授权

US08117250B2 VDSL2 transmitter/receiver architecture 有权
标题翻译： VDSL2发射机/接收机架构
公开(公告)号：US08117250B2
公开(公告)日：2012-02-14
申请号：US12159293
申请日：2006-12-29
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： G06F15/10
CPC分类号： G06F17/142 , H04L27/2628 , H04L27/265
摘要： The invention suggests a novel pipeline FFT/IFFT architecture that not only produces time-domain samples (after IFFT) but also pushes time-domain samples into FFT in a time-based sequential order. This reduces external memory requirement for buffering the time-domain samples. Also the design is based on a mixed radix-2 and radix-22 algorithm aiming at reducing number of multipliers and adders. Compared with other FFT/IFFT design methodologies such as radix-4, it achieves the minimum multiplier use, the minimum adder use and the minimum operating memory use. On the other hand, the design architecture not only can support different FFT/IFFT size required by different VDSL2 profiles but also utilizing a novel pipeline control mechanism to reduce logic switching at low-speed profiles. This effectively further reduces the power consumption at lower profiles and enables our VDSL2 digital chipsets to compete with ADSL2+ systems in terms of power consumption.
摘要翻译：本发明提出了一种新颖的流水线FFT / IFFT架构，其不仅产生时域采样（在IFFT之后），而且还以时间顺序的顺序将时域采样推入FFT。这减少了用于缓冲时域采样的外部存储器要求。此外，该设计是基于混合的radix-2和radix-22算法，旨在减少乘数和加法器的数量。与其他FFT / IFFT设计方法如radix-4相比，它实现了最小乘法器使用，最小加法器使用和最小操作内存使用。另一方面，设计架构不仅可以支持不同VDSL2配置文件所需的不同FFT / IFFT尺寸，还可以利用新颖的流水线控制机制来降低低速配置文件下的逻辑切换。这有效地进一步降低了功耗较低的功能，使我们的VDSL2数字芯片组在功耗方面与ADSL2 +系统竞争。

5. 发明授权

US08042032B2 Four-stage pipeline based VDSL2 Viterbi decoder 有权
标题翻译：基于VDSL2 Viterbi解码器的四级流水线
公开(公告)号：US08042032B2
公开(公告)日：2011-10-18
申请号：US12086850
申请日：2006-12-21
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： G06F11/00
CPC分类号： H03M13/4169 , H03M13/256
摘要： A novel method to divide the whole decoding process of the Viterbi decoder into four pipeline stages and the Viterbi decoder therefore. With an appropriate choice on the system clock, the invention trade-off the decoding speed with the hardware cost so that the designed Viterbi decoder is able to satisfy the decoding speed requirement for the highest speed profile in VDSL2 systems, 30 MHz profile. At the same time, with four-stage pipeline to just enough to meet the speed requirement, the hardware cost for the new designed Viterbi decoder is reduced compared with single-staged decoding.
摘要翻译：因此，将维特比解码器的整个解码处理分成四个流水线级和维特比解码器的新颖方法。通过对系统时钟的适当选择，本发明以硬件成本取代了解码速度，使得设计的维特比解码器能够满足VDSL2系统中最高速度配置文件的解码速度要求，30MHz配置文件。同时，采用四级流水线即可满足速度要求，与单级解码相比，新设计的维特比解码器的硬件成本降低。

6. 发明授权

US08111740B2 Time-domain equalizer 有权
标题翻译：时域均衡器
公开(公告)号：US08111740B2
公开(公告)日：2012-02-07
申请号：US12086968
申请日：2006-12-29
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： H04L27/01
CPC分类号： H04L25/03114 , H04L25/03133
摘要： The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.
摘要翻译：本发明提供了一种具有成本效益的TEQ硬件架构来支持多个VDSL2配置文件。它支持通过固件编程的可变TEQ分接长度。独特的设计支持低速配置文件下的更大的TEQ抽头长度，无需增加额外的乘数。支持的TEQ抽头的最大数量实际上与配置文件频率成反比。这完全满足了对于高速配置文件具有较长TEQ的低速配置和更短TEQ的要求。

7. 发明申请

US20090290629A1 Time-Domain Equalizer 有权
标题翻译：时域均衡器
公开(公告)号：US20090290629A1
公开(公告)日：2009-11-26
申请号：US12086968
申请日：2006-12-29
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： H04L27/01
CPC分类号： H04L25/03114 , H04L25/03133
摘要： The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.
摘要翻译：本发明提供了一种具有成本效益的TEQ硬件架构来支持多个VDSL2配置文件。它支持通过固件编程的可变TEQ分接长度。独特的设计支持低速配置文件下的更大的TEQ抽头长度，无需增加额外的乘数。支持的TEQ抽头的最大数量实际上与配置文件频率成反比。这完全满足了对于高速配置文件具有较长TEQ的低速配置和更短TEQ的要求。

8. 发明申请

US20090257540A1 Multi-Channel Timing Recovery System 有权
标题翻译：多通道定时恢复系统
公开(公告)号：US20090257540A1
公开(公告)日：2009-10-15
申请号：US12086895
申请日：2006-12-21
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H04L7/0337 , H04L27/2655 , H04L27/2675 , H04L27/2679
摘要： The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardware-based second-order timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop.
摘要翻译：本发明公开了一种利用共享CORDIC精确计算每个音调的相位的新型多通道定时恢复方案。然后，基于硬件的线性组合器模块用于从多个相位测量重建最佳相位估计。固件监视导频音的噪声方差，并确定每个音调的相应权重，以确保通过线性组合器实现最小相位抖动噪声。然后，基于硬件的二阶定时恢复控制环路产生VCXO或DCXO的频率参考信号。单个顺序控制的乘法器用于控制回路中的所有乘法。

9. 发明授权

US08094768B2 Multi-channel timing recovery system 有权
标题翻译：多通道定时恢复系统
公开(公告)号：US08094768B2
公开(公告)日：2012-01-10
申请号：US12086895
申请日：2006-12-21
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H04L7/0337 , H04L27/2655 , H04L27/2675 , H04L27/2679
摘要： The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardware-based second-order timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop.
摘要翻译：本发明公开了一种利用共享CORDIC精确计算每个音调的相位的新型多通道定时恢复方案。然后，基于硬件的线性组合器模块用于从多个相位测量重建最佳相位估计。固件监视导频音的噪声方差，并确定每个音调的相应权重，以确保通过线性组合器实现最小相位抖动噪声。然后，基于硬件的二阶定时恢复控制环路产生VCXO或DCXO的频率参考信号。单个顺序控制的乘法器用于控制回路中的所有乘法。

10. 发明申请

US20090063604A1 Vdsl2 Transmitter/Receiver Architecture 有权
标题翻译： Vdsl2发射机/接收机架构
公开(公告)号：US20090063604A1
公开(公告)日：2009-03-05
申请号：US12159293
申请日：2006-12-29
申请人： Yaolong Tan
发明人： Yaolong Tan
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L27/2628 , H04L27/265
摘要： The invention suggests a novel pipeline FFT/IFFT architecture that not only produces time-domain samples (after IFFT) but also pushes time-domain samples into FFT in a time-based sequential order. This reduces external memory requirement for buffering the time-domain samples. Also the design is based on a mixed radix-2 and radix-22 algorithm aiming at reducing number of multipliers and adders. Compared with other FFT/IFFT design methodologies such as radix-4, it achieves the minimum multiplier use, the minimum adder use and the minimum operating memory use. On the other hand, the design architecture not only can support different FFT/IFFT size required by different VDSL2 profiles but also utilizing a novel pipeline control mechanism to reduce logic switching at low-speed profiles. This effectively further reduces the power consumption at lower profiles and enables our VDSL2 digital chipsets to compete with ADSL2+ systems in terms of power consumption.
摘要翻译：本发明提出了一种新颖的流水线FFT / IFFT架构，其不仅产生时域采样（在IFFT之后），而且还以时间顺序的顺序将时域采样推入FFT。这减少了用于缓冲时域采样的外部存储器要求。此外，该设计是基于混合的radix-2和radix-22算法，旨在减少乘数和加法器的数量。与其他FFT / IFFT设计方法如radix-4相比，它实现了最小乘法器使用，最小加法器使用和最小操作内存使用。另一方面，设计架构不仅可以支持不同VDSL2配置文件所需的不同FFT / IFFT尺寸，还可以利用新颖的流水线控制机制来降低低速配置文件下的逻辑切换。这有效地进一步降低了功耗较低的功能，使我们的VDSL2数字芯片组在功耗方面与ADSL2 +系统竞争。

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