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1. 发明授权

US06970560B1 Method and apparatus for impairment diagnosis in communication systems 失效
标题翻译：通信系统中损伤诊断的方法和装置
公开(公告)号：US06970560B1
公开(公告)日：2005-11-29
申请号：US09710703
申请日：2000-11-10
申请人： John Josef Hench , Thorkell Gudmundsson , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Yaolong Tan , Harbinder Singh , Sunil C. Shah
发明人： John Josef Hench , Thorkell Gudmundsson , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Yaolong Tan , Harbinder Singh , Sunil C. Shah
IPC分类号： H04B3/46 , H04M1/76 , H04M3/08 , H04M3/18 , H04M3/30
CPC分类号： H04M3/085 , H04B3/487 , H04L5/0007 , H04L5/0046 , H04M3/18 , H04M3/304
摘要： Events that occur in a number of in domain communication channels where each channel is used by a communication service, are detected. A Bayesian Belief Network (BBN) defines a probabilistic cause-effect relationship between each cause and each effect on a victim channel. The probability of each of a number of possible causes as being a cause of interference in the victim channel is determined, by propagating observations of the interference backwards through the BBN.
摘要翻译：检测到在通信服务使用每个信道的域通信信道中的多个中发生的事件。贝叶斯信仰网络（BBN）定义了每个原因与每个对受害者信道的影响之间的概率因果关系。通过BBN向后传播干扰的观测来确定多个可能原因中的每一个作为受害信道干扰的原因的概率。

2. 发明授权

US06539536B1 Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics 有权
标题翻译：电子设计自动化系统和方法利用具有环回连接的多个单元组来模拟端口电气特性
公开(公告)号：US06539536B1
公开(公告)日：2003-03-25
申请号：US09496967
申请日：2000-02-02
申请人： Harbinder Singh , Denis Martin , Srinivas Ajjarapu , Robert Walker
发明人： Harbinder Singh , Denis Martin , Srinivas Ajjarapu , Robert Walker
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A computer implemented process and system for electronic design automation (EDA) using groups of multiple cells having loop-back connections for modeling port electrical characteristics. Multi-bit cells have multiple gates of the same function implemented within a same cell. Multi-bit components have multiple multi-bit cells implemented within a same component. Scannable multi-bit cells and components are similar to multi-bit cells and components but contain scannable sequential elements with scan chains installed. Multi-bit cells may or may not have each sequential cells' input and each sequential cells' output available externally. The scannable sequential elements of a multi-bit component are ordered into a predefined scan chain which is defined by the library containing the multi-bit component or multi-bit cell. During scan replacement processes of the EDA compile process, multi-bit cells and components of the netlist are replaced with scannable multi-bit cells and components. Also, during optimization, multi-bit cells and components undergo equivalence replacement to meet specified constraints (e.g., area, performance, etc.). To model the electrical characteristics of the port during certain optimizations, loopback connections are applied to the multi-bit components from the scan out port to the scan in port of the multi-bit cell or component, therefore, one loopback connection spans multiple sequential cells within the multi-bit cell or component. During certain optimizations, loopback connections are applied to multiple sequential cells that are coupled together but do not necessarily reside in a multi-bit cell or component. By spanning multiple sequential cells, circuit degeneration is reduced thereby providing better circuit optimizations for netlists having scan circuitry.
摘要翻译：一种用于电子设计自动化（EDA）的计算机实现的过程和系统，其使用具有用于建模端口电特性的环回连接的多个单元组。多位单元具有在相同单元内实现的具有相同功能的多个门。多位组件具有在相同组件内实现的多个多位单元。可扫描的多位单元和组件类似于多位单元和组件，但是包含可扫描顺序元件，并安装了扫描链。多位单元可以具有或不具有每个顺序单元的输入，并且每个顺序单元的输出可从外部获得。多位组件的可扫描顺序元素被排序到由包含多位组件或多位单元的库定义的预定义扫描链中。在EDA编译过程的扫描替换过程中，网表的多位单元和组件被可扫描的多位单元和组件替代。此外，在优化期间，多位单元和组件进行等价替换以满足指定的约束（例如，面积，性能等）。为了在某些优化期间对端口的电气特性进行建模，环回连接被应用于多位组件从多位单元或组件的扫描输出端口到扫描端口，因此一个环回连接跨越多个连续单元在多位单元或组件内。在某些优化期间，环回连接被应用于耦合在一起但不一定驻留在多位单元或组件中的多个顺序单元。通过跨越多个顺序单元，电路退化被减少，从而为具有扫描电路的网表提供更好的电路优化。

3. 发明授权

US06449755B1 Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker 有权
标题翻译： IEEE 1149.1符合性检查器中的指令签名和主输入和主输出提取
公开(公告)号：US06449755B1
公开(公告)日：2002-09-10
申请号：US09616388
申请日：2000-07-14
申请人： James Beausang , Harbinder Singh
发明人： James Beausang , Harbinder Singh
IPC分类号： G06F1750
CPC分类号： G01R31/318591
摘要： A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.
摘要翻译：一种用于从网表自动提取IEEE 1149.1标准设计并执行合规性检查的计算机化方法和系统。本发明接收网表的TAP（测试接入端口）描述和兼容性使能端口。提取TAP控制器，其状态端口被识别，在边界扫描设计数据库（BSDD）中被引用，并且其状态被验证。控制TAP控制器，使得指令寄存器位于BSDD中并被引用。控制TAP控制器，以便找到旁路寄存器并更新BSDD。控制TAP控制器，使得边界扫描寄存器（BSR）的移位和更新单元被发现，控制，输入和输出BSR单元被表征，BSDD被更新。还推断了主输入和输出信息，并找到了device_ID寄存器。前端引脚用于定位剩余指令的签名，并找到其测试数据寄存器。为了推断SAMPLE指令，选择BSR的指令是组，并且没有表现出SAMPLE指令行为的指令被消除。然后推断主输入和主输出。然后推断以下说明：INTEST，HIGHZ，CLAMP，IDCODE和RUNBIST。由于IEEE 1149.1设计的每个上述元件都位于其中，所以它们被用于更新BSDD，并且本身也被固有地验证了本发明的符合性。不符合标准的违规设计。

4. 发明授权

US06311317B1 Pre-synthesis test point insertion 有权
标题翻译：预合成测试点插入
公开(公告)号：US06311317B1
公开(公告)日：2001-10-30
申请号：US09282304
申请日：1999-03-31
申请人： Ajay Khoche , Harbinder Singh , Dhiraj Goswami , Denis Martin
发明人： Ajay Khoche , Harbinder Singh , Dhiraj Goswami , Denis Martin
IPC分类号： G06F1750
CPC分类号： G01R31/3185 , G06F17/5045
摘要： A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.
摘要翻译：在集成电路设计中插入测试点的方法和系统。根据本发明，在电子设计过程的早期以及在逻辑合成之前插入测试点，使得可以避免设计约束违规的问题。本发明的一个实施例包括计算机实现的接收集成电路设计的未映射网表的步骤，以及从外部源接收指示要插入的测试点的位置和期望功能的数据。此后，本发明在所指示的位置插入通用测试点电路，并生成修改的未映射网表。随后，本发明对经修改的未映射网表执行逻辑合成处理，其中通用测试点电路退化为用于执行所需功能的实际测试点电路。实际的测试点电路也可以与集成电路的其他电路合并以产生更有效的设计。

5. 发明授权

US06870901B1 Design and architecture of an impairment diagnosis system for use in communications systems 失效
标题翻译：用于通信系统的损伤诊断系统的设计和架构
公开(公告)号：US06870901B1
公开(公告)日：2005-03-22
申请号：US09711684
申请日：2000-11-10
申请人： Thorkell Gudmundsson , John Josef Hench , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Harbinder Singh , Yaolong Tan , Sunil C. Shah
发明人： Thorkell Gudmundsson , John Josef Hench , Amir Gholamhossein Zadeh Aghdam , Ioannis Kanellakopoulos , Gurcan Aral , Harbinder Singh , Yaolong Tan , Sunil C. Shah
IPC分类号： H04B3/32 , H04L1/24 , H04L12/24 , H04L25/02 , H04L25/03 , H04L27/26 , H04M3/24 , H04M3/30 , H04M3/36 , H05M1/24 , H04L12/42
CPC分类号： H04L41/046 , H04B3/32 , H04L1/24 , H04L25/0204 , H04L25/03305 , H04L27/2608 , H04L41/0631 , H04L41/142 , H04L41/145 , H04L2025/03414 , H04M3/247 , H04M3/306 , H04M3/36
摘要： A method and apparatus are disclosed. The method includes one or more of the following: compiling statistical models of physical layers of a communications system; creating a priori distributions of cross-talk transfer functions; storing the models and the a priori distribution in a storage medium; and using the models and the a priori distributions to diagnose probable causes of events detected in said communications system.
摘要翻译：公开了一种方法和装置。该方法包括以下一个或多个：编译通信系统的物理层的统计模型; 创建串扰传递函数的先验分布; 将模型和先验分布存储在存储介质中; 以及使用所述模型和先验分布来诊断在所述通信系统中检测到的事件的可能原因。

6. 发明授权

US6141790A Instructions signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker 失效
标题翻译： IEEE 1149.1符合性检查器中的指令签名和主输入和主输出提取
公开(公告)号：US6141790A
公开(公告)日：2000-10-31
申请号：US960853
申请日：1997-10-30
申请人： James Beausang , Harbinder Singh
发明人： James Beausang , Harbinder Singh
IPC分类号： G01R31/3185 , G06F17/50 , G01R31/303 , G01R31/3187
CPC分类号： G01R31/318591
摘要： A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.
摘要翻译：一种用于从网表自动提取IEEE 1149.1标准设计并执行合规性检查的计算机化方法和系统。本发明接收网表的TAP（测试接入端口）描述和兼容性使能端口。提取TAP控制器，其状态端口被识别，在边界扫描设计数据库（BSDD）中被引用，并且其状态被验证。控制TAP控制器，使得指令寄存器位于BSDD中并被引用。控制TAP控制器，以便找到旁路寄存器并更新BSDD。控制TAP控制器，使得边界扫描寄存器（BSR）的移位和更新单元被发现，控制，输入和输出BSR单元被表征，BSDD被更新。还推断出主输入和输出信息，并找到设备ID寄存器。前端引脚用于定位剩余指令的签名，并找到其测试数据寄存器。为了推断SAMPLE指令，选择BSR的指令是组，并且没有表现出SAMPLE指令行为的指令被消除。然后推断主输入和主输出。然后推断以下说明：INTEST，HIGHZ，CLAMP，IDCODE和RUNBIST。由于IEEE 1149.1设计的每个上述元件都位于其中，所以它们被用于更新BSDD，并且本身也被固有地验证了本发明的符合性。不符合标准的违规设计。

7. 发明授权

US6012155A Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist 失效
标题翻译：在网表内执行IEEE 1149.1标准设计的自动提取和合规性检查的方法和系统
公开(公告)号：US6012155A
公开(公告)日：2000-01-04
申请号：US961389
申请日：1997-10-30
申请人： James Beausang , Harbinder Singh
发明人： James Beausang , Harbinder Singh
IPC分类号： G01R31/3185 , G06F7/24
CPC分类号： G01R31/318583
摘要： A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.
摘要翻译：一种用于从网表自动提取IEEE 1149.1标准设计并执行合规性检查的计算机化方法和系统。本发明接收网表的TAP（测试接入端口）描述和兼容性使能端口。提取TAP控制器，其状态端口被识别，在边界扫描设计数据库（BSDD）中被引用，并且其状态被验证。控制TAP控制器，使得指令寄存器位于BSDD中并被引用。控制TAP控制器，以便找到旁路寄存器并更新BSDD。控制TAP控制器，使得边界扫描寄存器（BSR）的移位和更新单元被发现，控制，输入和输出BSR单元被表征，BSDD被更新。还推断出主输入和输出信息，并找到设备ID寄存器。前端引脚用于定位剩余指令的签名，并找到其测试数据寄存器。为了推断SAMPLE指令，选择BSR的指令是组，并且没有表现出SAMPLE指令行为的指令被消除。然后推断主输入和主输出。然后推断以下说明：INTEST，HIGHZ，CLAMP，IDCODE和RUNBIST。由于IEEE 1149.1设计的每个上述元件都位于其中，所以它们被用于更新BSDD，并且本身也被固有地验证了本发明的符合性。不符合标准的违规设计。

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