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1. 发明授权

US06300658B1 Method for reduced gate aspect ration to improve gap-fill after spacer etch 有权
标题翻译：减少栅极比例的方法，以改善间隔蚀刻后的间隙填充
公开(公告)号：US06300658B1
公开(公告)日：2001-10-09
申请号：US09368073
申请日：1999-08-03
申请人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
发明人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76837 , H01L27/115
摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
摘要翻译：本发明提供一种降低闪速存储器件的栅极纵横比的方法。该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。因此提高了装置的可靠性。

2. 发明授权

US06376309B2 Method for reduced gate aspect ratio to improve gap-fill after spacer etch 有权
标题翻译：减小栅极纵横比以改善间隔物刻蚀之后的间隙填充的方法
公开(公告)号：US06376309B2
公开(公告)日：2002-04-23
申请号：US09811288
申请日：2001-03-16
申请人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
发明人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76837 , H01L27/115
摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
摘要翻译：本发明提供一种降低闪速存储器件的栅极纵横比的方法。该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。因此提高了装置的可靠性。

3. 发明授权

US06445051B1 Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权
标题翻译：用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限
公开(公告)号：US06445051B1
公开(公告)日：2002-09-03
申请号：US09563797
申请日：2000-05-02
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28273
摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供多个触点的方法和系统。闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。该方法和系统还包括蚀刻绝缘层以提供多个接触孔。绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤不会蚀刻穿过多个场绝缘区域。该方法和系统还包括用导体填充多个接触孔。

4. 发明授权

US06410458B1 Method and system for eliminating voids in a semiconductor device 有权
标题翻译：用于消除半导体器件中的空隙的方法和系统
公开(公告)号：US06410458B1
公开(公告)日：2002-06-25
申请号：US09494755
申请日：2000-01-31
申请人： Lu You , Dawn Hopper , John Jianshi Wang
发明人： Lu You , Dawn Hopper , John Jianshi Wang
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/76837 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a method and system for eliminating voids in a semiconductor device. The method comprises the steps of forming metal lines over a semiconductor substrate, forming a first oxide layer utilizing a high density plasma deposition technique, forming a second oxide layer utilizing a carbon free resin and forming a topside dielectric layer. Through the use of a method in accordance with the present invention, the voids that are created in the dielectric films during conventional semiconductor processing methodology are eliminated. The use of a high density plasma deposition technique provides a more directional deposition that can get between metal lines that are separated by smaller gaps. The dielectric films are thereby strengthened, which increases the reliability of the semiconductor device. Furthermore, by utilizing hydrogen silsesquiloxane instead of a conventional spin-on glass, there is no concern regarding carbon contamination since hydrogen silsesquiloxane doesn't contain carbon atoms.
摘要翻译：本发明是用于消除半导体器件中的空隙的方法和系统。该方法包括以下步骤：在半导体衬底上形成金属线，利用高密度等离子体沉积技术形成第一氧化物层，利用无碳树脂形成第二氧化物层并形成顶层电介质层。通过使用根据本发明的方法，消除了在常规半导体处理方法中在电介质膜中产生的空隙。使用高密度等离子体沉积技术提供了更多的定向沉积，其可以在由较小间隙分离的金属线之间获得。因此，介电膜被加强，这增加了半导体器件的可靠性。此外，通过使用氢硅氧烷代替常规旋涂玻璃，由于氢硅氧烷不含碳原子，因此不关心碳污染。

5. 发明授权

US06638358B1 Method and system for processing a semiconductor device 失效
标题翻译：用于处理半导体器件的方法和系统
公开(公告)号：US06638358B1
公开(公告)日：2003-10-28
申请号：US09483176
申请日：2000-01-13
申请人： Lu You , Mark S. Chang , Hao Fang
发明人： Lu You , Mark S. Chang , Hao Fang
IPC分类号： B05C500
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124 , H01L21/316 , H01L21/823468
摘要： The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450° C. Through the use of a system/method in accordance with the present invention, the voids that are created in the spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers posses the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.
摘要翻译：本发明是用于处理半导体器件的方法和系统，该半导体器件包括至少两个栅极叠层和间隔物间隙。该方法和系统包括利用晶体管器件级上的旋涂技术在间隔物间隙中提供氧化物隔离物，然后在高于约450℃的温度下固化半导体器件。通过使用根据本发明的系统/方法利用本发明，消除了在常规半导体处理期间在间隔物间隙中产生的空隙。此外，氧化物间隔物具有通常通过使用常规CVD方法提供的高质量特性。因此，通过使用根据本发明的系统/方法的结果，MOSFET氧化物间隔物被加强，这增加了半导体器件的可靠性。

6. 发明授权

US06448594B1 Method and system for processing a semiconductor device 有权
标题翻译：用于处理半导体器件的方法和系统
公开(公告)号：US06448594B1
公开(公告)日：2002-09-10
申请号：US09539307
申请日：2000-03-30
申请人： Maria C. Chan , Hao Fang , Lu You , Mark S. Chang , King Wai Kelwin Ko
发明人： Maria C. Chan , Hao Fang , Lu You , Mark S. Chang , King Wai Kelwin Ko
IPC分类号： H01L2976
CPC分类号： H01L21/823468 , H01L21/823425 , Y10S257/90
摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.
摘要翻译：在本发明的第一方面中，公开了一种半导体器件。半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物栅堆叠，其中所述至少一个氧化物间隔物是三角形的。通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

7. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

8. 发明申请

US20080108193A1 Cu annealing for improved data retention in flash memory devices 有权
标题翻译： Cu退火以改善闪存器件中的数据保留
公开(公告)号：US20080108193A1
公开(公告)日：2008-05-08
申请号：US11593086
申请日：2006-11-06
申请人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
发明人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/76883 , H01L27/11521
摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.
摘要翻译：通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。实施方案包括在含有低H 2 N 2或无H 2 N的N 2 O 2气氛中以及在低于200℃的温度下退火嵌入的Cu，例如，100℃至150℃

9. 发明申请

US20080096364A1 Conformal liner for gap-filling 审中-公开
标题翻译：用于间隙填充的保形衬套
公开(公告)号：US20080096364A1
公开(公告)日：2008-04-24
申请号：US11582442
申请日：2006-10-18
申请人： Erik Wilson , Minh-Van Ngo , Hieu Pham , Robert Huertas , Lu You , Hirokazu Tokuno , Alexander Nickel , Minh Tran
发明人： Erik Wilson , Minh-Van Ngo , Hieu Pham , Robert Huertas , Lu You , Hirokazu Tokuno , Alexander Nickel , Minh Tran
IPC分类号： H01L21/76
CPC分类号： H01L21/823468 , H01L21/76829 , H01L21/76837 , H01L21/823437
摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.
摘要翻译：通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

10. 发明授权

US07309650B1 Memory device having a nanocrystal charge storage region and method 有权
标题翻译：具有纳米晶体电荷存储区域和方法的存储器件
公开(公告)号：US07309650B1
公开(公告)日：2007-12-18
申请号：US11065388
申请日：2005-02-24
申请人： Connie Pin-Chin Wang , Lu You , Zoran Krivokapic , Paul Raymond Besser , Suzette Keefe Pangrle
发明人： Connie Pin-Chin Wang , Lu You , Zoran Krivokapic , Paul Raymond Besser , Suzette Keefe Pangrle
IPC分类号： H01L21/44
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/28273 , H01L29/42332
摘要： A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.
摘要翻译：一种具有金属纳米晶体电荷存储结构的存储器件及其制造方法。存储器件可以通过在半导体衬底上形成第一氧化物层，然后在氧化物层上设置多孔介电层并在第二氧化物层上设置第二氧化物层来制造。在第二介电材料层上形成一层导电材料。在导电材料上形成蚀刻掩模。导电材料和下面的介电层被各向异性地蚀刻以形成其上设置有栅电极的电介质结构。在介电结构和栅电极上形成金属层，并处理金属层的一部分扩散到多孔介电层中。然后去除金属层。

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