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1. 发明授权

US06747472B2 Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same 有权
标题翻译：用于微连接互连的测试和烧录的临时装置连接结构及其制造方法
公开(公告)号：US06747472B2
公开(公告)日：2004-06-08
申请号：US10052619
申请日：2002-01-18
申请人： John Harold Magerlein , Samuel Roy McKnight , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Joseph J. Van Horn , Richard Paul Volant , George Frederick Walker
发明人： John Harold Magerlein , Samuel Roy McKnight , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Joseph J. Van Horn , Richard Paul Volant , George Frederick Walker
IPC分类号： G01R3126
CPC分类号： H01L24/11 , G01R1/0416 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H05K3/244 , H05K3/325 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.
摘要翻译：一种用于通过将装置芯片临时附接到具有多个具有微树突状特征的容器的载体来测试装置芯片集合的系统; 所述插座与所述器件芯片上的匹配的接触焊盘组匹配并且与所述插座接触; 所述载体另外具有通过互连布线连接到插座的测试垫。该系统允许将芯片连接在一起，并通过探测载体上的测试垫来整体测试集合。芯片集合的老化也可以在临时载体上执行，这是可重复使用的。

2. 发明授权

US06661098B2 High density area array solder microjoining interconnect structure and fabrication method 有权
标题翻译：高密度区阵列焊料微接合互连结构及制造方法
公开(公告)号：US06661098B2
公开(公告)日：2003-12-09
申请号：US10052620
申请日：2002-01-18
申请人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
发明人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L21/67144 , H01L23/49811 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01046 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/34 , H05K3/3436 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H01L2924/00
摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
摘要翻译：教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片的阵列包括粘附层，阻挡层和易熔焊料层的微接合焊盘阵列，焊盘位于相对于屏障插座的匹配位置; 所述器件芯片通过微接点阵列连接到所述载体，导致能够实现非常高的输入/输出密度和芯片间布线密度的互连。

3. 发明授权

US06819000B2 High density area array solder microjoining interconnect structure and fabrication method 有权
标题翻译：高密度区阵列焊料微接合互连结构及制造方法
公开(公告)号：US06819000B2
公开(公告)日：2004-11-16
申请号：US10692065
申请日：2003-10-23
申请人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
发明人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L21/67144 , H01L23/49811 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01046 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/34 , H05K3/3436 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H01L2924/00
摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
摘要翻译：教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片采用微连接焊盘阵列，其包括粘附层，阻挡层和易熔焊料层，焊盘位于相对于阻挡插座的匹配位置; 器件芯片通过微接点阵列连接到载体，导致能够具有非常高的输入/输出密度和芯片间布线密度的互连。

4. 发明授权

US06732908B2 High density raised stud microjoining system and methods of fabricating the same 有权
标题翻译：高密度凸起螺柱微接合系统及其制造方法
公开(公告)号：US06732908B2
公开(公告)日：2004-05-11
申请号：US10052591
申请日：2002-01-18
申请人： Bruce Kenneth Furman , Maheswaran Surendra , Sherif A. Goma , Simon M. Karecki , John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
发明人： Bruce Kenneth Furman , Maheswaran Surendra , Sherif A. Goma , Simon M. Karecki , John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
IPC分类号： B23K3102
CPC分类号： H01L24/12 , H01L21/288 , H01L21/2885 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05571 , H01L2224/05599 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/13582 , H01L2224/13616 , H01L2224/13644 , H01L2224/13655 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H05K2201/10674 , H01L2224/45111 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.
摘要翻译：一个微型接头互连结构，包括具有精确可控高度的密集阵列的金属螺柱，并具有接合冶金。该阵列在要连接到载体的装置芯片上或与其他装置一起在载体上产生，其中一些装置芯片可被选择为具有相似的互连结构，以便将组装的载体形成为一体，完整的计算，通信或网络系统。

5. 发明申请

US20090302454A1 Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer 审中-公开
标题翻译：用于通过基板晶片制造具有完全金属化通孔的封装接口基板晶片的技术
公开(公告)号：US20090302454A1
公开(公告)日：2009-12-10
申请号：US12462980
申请日：2009-08-11
申请人： Yu- Ting Cheng , Sherif A. Goma , John Harold Magerlein , Sampath Purushothaman , Carlos Juan Sambucetti , George Frederick Walker
发明人： Yu- Ting Cheng , Sherif A. Goma , John Harold Magerlein , Sampath Purushothaman , Carlos Juan Sambucetti , George Frederick Walker
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H05K3/422 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H01L2924/3011 , H05K1/0306 , H05K2201/09563 , H05K2201/10378 , H05K2203/025 , H01L2924/00
摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.
摘要翻译：本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

6. 发明授权

US07880305B2 Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer 有权
标题翻译：用于通过基板晶片制造具有完全金属化通孔的封装接口基板晶片的技术
公开(公告)号：US07880305B2
公开(公告)日：2011-02-01
申请号：US10290049
申请日：2002-11-07
申请人： Yu-Ting Cheng , Sherif A. Goma , John Harold Magerlein , Sampath Purushothaman , Carlos Juan Sambucetti , George Frederick Walker
发明人： Yu-Ting Cheng , Sherif A. Goma , John Harold Magerlein , Sampath Purushothaman , Carlos Juan Sambucetti , George Frederick Walker
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K3/422 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H01L2924/3011 , H05K1/0306 , H05K2201/09563 , H05K2201/10378 , H05K2203/025 , H01L2924/00
摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.
摘要翻译：本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

7. 发明授权

US06646345B2 Method for forming Co-W-P-Au films 有权
公开(公告)号：US06646345B2
公开(公告)日：2003-11-11
申请号：US09966629
申请日：2001-09-27
申请人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
发明人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , C23C18/1651 , C23C18/1841 , C23C18/44 , C23C18/50 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76864 , H01L21/76874 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

8. 发明授权

US06323128B1 Method for forming Co-W-P-Au films 失效
标题翻译： Co-W-P-Au薄膜的制备方法
公开(公告)号：US06323128B1
公开(公告)日：2001-11-27
申请号：US09320499
申请日：1999-05-26
申请人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
发明人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
IPC分类号： H01L21441
CPC分类号： H01L21/76846 , C23C18/1651 , C23C18/1841 , C23C18/44 , C23C18/50 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76864 , H01L21/76874 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.
摘要翻译：公开了一种用于在半导体结构中的铜互连上用作扩散阻挡层的Co-W-P-Au的四元合金膜的形成方法和包含这种膜的器件。在该方法中，首先通过两个单独的预处理步骤对具有铜导电区域的基板进行预处理。在第一步骤中，将衬底浸入H 2 SO 4冲洗溶液中，接着在含有钯离子的溶液中浸渍一段足以使离子沉积在铜导电区域表面上的时间。然后将基底浸入含有至少15g / l柠檬酸钠或EDTA的溶液中，以从铜导电区域的表面除去过量的钯离子。在通过蒸馏水在第一冲洗步骤中冲洗预处理的基材之后，在包含钴离子，钨酸根离子，柠檬酸根离子的第一电镀液中，在铜导电区域的表面上化学镀Co-WP膜和还原剂。在用Co-W-P膜涂布的基材在第二次漂洗步骤中用蒸馏水冲洗后，将基板浸渍在Co-W-P膜顶部沉积Au层的第二无电镀液中。本发明的新型四元合金膜可以用作铜互连和硅衬底或SiO 2电介质层之间的有效扩散阻挡层。

9. 发明申请

US20090142924A1 REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF CU WIRES BY SURFACE COATING 审中-公开
标题翻译：通过表面涂层降低CU电线的电导率和受压感应迁移
公开(公告)号：US20090142924A1
公开(公告)日：2009-06-04
申请号：US12341856
申请日：2008-12-22
申请人： Chao-Kun Hu , Robert Rosenberg , Judith Marie Rubino , Carlos Juan Sambucetti , Anthony Kendall Stamper
发明人： Chao-Kun Hu , Robert Rosenberg , Judith Marie Rubino , Carlos Juan Sambucetti , Anthony Kendall Stamper
IPC分类号： H01L21/441
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76864 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.
摘要翻译：本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。该涂层足够薄，以便消除对通过抛光的附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已被发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热压力消除。此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。

10. 发明授权

US6105852A Etched glass solder bump transfer for flip chip integrated circuit devices 失效
标题翻译：蚀刻玻璃焊料凸块传输用于倒装芯片集成电路器件
公开(公告)号：US6105852A
公开(公告)日：2000-08-22
申请号：US19396
申请日：1998-02-05
申请人： Steven A. Cordes , Peter Alfred Gruber , Egon Max Kummer , Stephen Roux , Carlos Juan Sambucetti , James Louis Speidell
发明人： Steven A. Cordes , Peter Alfred Gruber , Egon Max Kummer , Stephen Roux , Carlos Juan Sambucetti , James Louis Speidell
IPC分类号： B23K35/12 , H01L21/60 , H05K3/00 , H05K3/34 , H01L29/40 , H01L2/44
CPC分类号： H01L24/11 , H05K3/3468 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K2203/0113 , H05K2203/0338 , H05K2203/128 , H05K3/002
摘要： A precise volume, precisely registerable carrier is provided for use with injection molding for producing integrated circuit bump contacts in the "flip chip" technology. A hemispherical cavity is produced by etching through and undercutting a registered opening into a transparent carrier. The hemispherical cavity has related specific volume and visible peripheral shape that permits simple optical quality control when the injection molding operation has filled the cavity and simple optical registration for fusing to the pads on the integrated circuit.
摘要翻译：提供精确的体积，精确对准的载体，用于注射成型，用于在“倒装芯片”技术中制造集成电路凸块触点。通过将注册的开口蚀刻穿透并切割成透明载体来制造半球形腔。半球形腔体具有相关的体积和可见的周边形状，当注射成型操作已经填充空腔时，允许简单的光学质量控制，并且简单的光学配准用于熔合到集成电路上的焊盘。

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