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1. 发明授权

US06719884B2 Method of manufacturing optical devices and related improvements 有权
标题翻译：制造光学器件的方法及相关改进
公开(公告)号：US06719884B2
公开(公告)日：2004-04-13
申请号：US10047308
申请日：2002-01-15
申请人： John Haig Marsh , Craig James Hamilton , Olek Peter Kowalski , Stuart Duncan McDougall , Xuefeng Liu , Bo-Cang Qui
发明人： John Haig Marsh , Craig James Hamilton , Olek Peter Kowalski , Stuart Duncan McDougall , Xuefeng Liu , Bo-Cang Qui
IPC分类号： C23C1434
CPC分类号： B82Y20/00 , H01L21/182 , H01S5/3413
摘要： A method of manufacturing an optical device, wherein the device body portion from which the device is to be made includes at least one Quantum Well, the method including the step of causing an impurity material including copper to intermix with the Quantum Well.
摘要翻译：一种制造光学器件的方法，其中将要制造器件的器件主体部分包括至少一个量子阱，该方法包括使包括铜的杂质材料与量子阱混合的步骤。

2. 发明申请

US20110102537A1 Thermal printing with laser activation 审中-公开
标题翻译：激光激光热敏打印
公开(公告)号：US20110102537A1
公开(公告)日：2011-05-05
申请号：US11596734
申请日：2005-05-19
申请人： Neil Griffin , Samuel Charles William Hyde , Anthony Hailes , Keith Turner , Nicholas James Wooder , John Haig Marsh , Stephen Gorton , Christopher Humby , Gary Ternent , Eric Goutain , Xuefeng Liu , Alexander Ballantyne
发明人： Neil Griffin , Samuel Charles William Hyde , Anthony Hailes , Keith Turner , Nicholas James Wooder , John Haig Marsh , Stephen Gorton , Christopher Humby , Gary Ternent , Eric Goutain , Xuefeng Liu , Alexander Ballantyne
IPC分类号： B41J2/435
CPC分类号： H04N1/40031 , B41J2/45 , B41J2/4753 , H01S5/06804 , H01S5/4025 , H04N1/1932 , H04N1/1934 , H04N1/40043 , H04N1/4005
摘要： Methods and apparatus for implementing thermal printing techniques onto thermally sensitive print media use one or more laser arrays to provide optical heating. Thermal management of the laser arrays is described. Techniques for alignment of multiple monolithic arrays onto a common carrier are described. Various output optics are described.
摘要翻译：在热敏打印介质上实施热敏打印技术的方法和设备使用一个或多个激光阵列来提供光学加热。描述了激光阵列的热管理。描述了将多个单片阵列对准到公共载体上的技术。描述各种输出光学器件。

3. 发明授权

US09448162B2 Time-resolved single-photon or ultra-weak light multi-dimensional imaging spectrum system and method 有权
标题翻译：时间分辨单光子或超弱光多维成像光谱系统及方法
公开(公告)号：US09448162B2
公开(公告)日：2016-09-20
申请号：US14351028
申请日：2012-05-14
申请人： Guangjie Zhai , Wenkai Yu , Xuefeng Liu , Xuri Yao , Chao Wang , Zhibin Sun
发明人： Guangjie Zhai , Wenkai Yu , Xuefeng Liu , Xuri Yao , Chao Wang , Zhibin Sun
IPC分类号： G01N21/25 , G01N21/64 , G01N21/17 , H03K21/38 , G01J1/04 , G01J1/42 , G01S17/89 , G01S7/481 , G01S7/486 , G02B26/08
CPC分类号： G01N21/255 , G01J1/0414 , G01J1/4228 , G01N21/17 , G01N21/6456 , G01S7/4816 , G01S7/486 , G01S17/89 , G02B26/0833 , H03K21/38
摘要： A single-photon or ultra-weak light multi-D imaging spectral system and method. In order to realize rough time resolution, a time-resolved single-photon counting 2D imaging system for forming color or grey imaging is provided. Moreover, in order to realize high-precision time resolution, the system comprises a light source, an imaging spectral measurement unit, an electric detection unit, a system control unit and an algorithm unit. The light carrying information of an object is imaged on a spatial light modulator and randomly modulated according to compressed sensing theory, emergent light of a grating is collected using a point or array single-photon detector, the number of photons and photon arrival time are recorded, and reconstruction is carried out using the compressed sensing algorithm and related algorithm of the spectral imaging. The system provides single-photon detection sensitivity, high time resolution and wide spectral range, and can be applied in numerous new high-tech industries.
摘要翻译：单光子或超弱光多D成像光谱系统及方法。为了实现粗糙的时间分辨率，提供了用于形成彩色或灰度成像的时间分辨的单光子计数2D成像系统。此外，为了实现高精度时间分辨率，该系统包括光源，成像光谱测量单元，电检测单元，系统控制单元和算法单元。物体的光携带信息在空间光调制器上成像，并且根据压缩感测理论随机调制，使用点或阵列单光子检测器收集光栅的出射光，记录光子数和光子到达时间，并利用压缩感知算法和相关的光谱成像算法进行重建。该系统提供单光子检测灵敏度高，时间分辨率高，光谱范围广，可应用于众多新兴高科技行业。

4. 发明授权

US09080990B2 Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements 有权
标题翻译：计量系统的照明子系统，计量系统以及用于计量测量的照明样本的方法
公开(公告)号：US09080990B2
公开(公告)日：2015-07-14
申请号：US13061936
申请日：2009-09-29
申请人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
发明人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
IPC分类号： G01N21/55 , G01N21/95 , G01N21/47
CPC分类号： G01N21/9501 , G01N2021/479
摘要： Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements are provided. One illumination subsystem includes a light source configured to generate coherent pulses of light and a dispersive element positioned in the path of the coherent pulses of light, which is configured to reduce coherence of the pulses of light by mixing spatial and temporal characteristics of light distribution in the pulses of light. The illumination subsystem also includes an electro-optic modulator positioned in the path of the pulses of light exiting the dispersive element and which is configured to reduce the coherence of the pulses of light by temporally modulating the light distribution in the pulses of light. The illumination subsystem is configured to direct the pulses of light from the electro-optic modulator to a specimen positioned in the metrology system.
摘要翻译：提供了计量系统的照明子系统，计量系统和用于度量测量的照明样本的方法。一个照明子系统包括被配置为产生相干的光脉冲的光源和位于相干脉冲光的路径中的色散元件，该色散元件被配置为通过将光分布的空间和时间特征混合在一起来减小光脉冲的相干性光的脉冲。照明子系统还包括位于离开色散元件的光的脉冲的路径中的电光调制器，其被配置为通过暂时调制光脉冲中的光分布来减小光脉冲的相干性。照明子系统被配置为将来自电光调制器的光的脉冲引导到位于计量系统中的样本。

5. 发明授权

US09059138B2 Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
标题翻译：具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构
公开(公告)号：US09059138B2
公开(公告)日：2015-06-16
申请号：US13358180
申请日：2012-01-25
申请人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
发明人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
IPC分类号： H01L29/737 , G06F17/50 , H01L21/331 , H01L29/417 , H01L29/66 , H01L29/10
CPC分类号： H01L29/417 , H01L29/1004 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.
摘要翻译：提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。收集器触点有利地延伸穿过外部基极层的至少一部分。

6. 发明授权

US08946013B2 Lateral diffusion field effect transistor with drain region self-aligned to gate electrode 有权
标题翻译：侧向扩散场效应晶体管，漏极区自对准至栅电极
公开(公告)号：US08946013B2
公开(公告)日：2015-02-03
申请号：US13364663
申请日：2012-02-02
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/00 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/10
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

7. 发明授权

US08860191B2 On-chip transmission line structures with balanced phase delay 有权
标题翻译：具有平衡相位延迟的片上传输线结构
公开(公告)号：US08860191B2
公开(公告)日：2014-10-14
申请号：US13168512
申请日：2011-06-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L23/66 , H01P1/18 , H01L23/522
CPC分类号： H01L23/5222 , H01L23/5225 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01P1/184 , Y10T29/49117 , H01L2924/00
摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.
摘要翻译：一种传输线路结构，相关设计结构及其相关方法。公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为基本上与第二部分相同。

8. 发明授权

US08754455B2 Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure 有权
标题翻译：具有P型硅锗或硅碳化硅栅的结型场效应晶体管结构和形成该结构的方法
公开(公告)号：US08754455B2
公开(公告)日：2014-06-17
申请号：US12983489
申请日：2011-01-03
申请人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
发明人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
IPC分类号： H01L29/80
CPC分类号： H01L29/66916 , H01L27/14679 , H01L29/0649 , H01L29/16 , H01L29/42316 , H01L29/66462 , H01L29/808 , H01L29/8086
摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
摘要翻译：公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性）。通过明确定义该结，N型沟道区中的耗尽层延伸。延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。本文还公开了形成这种JFET结构的方法的实施例。

9. 发明申请

US20130309681A1 Immortalization of Epithelial Cells and Methods of Use 有权
公开(公告)号：US20130309681A1
公开(公告)日：2013-11-21
申请号：US13885078
申请日：2011-11-11
申请人： Richard Schlegel , Xuefeng Liu
发明人： Richard Schlegel , Xuefeng Liu
IPC分类号： C12N5/071
CPC分类号： C12N5/0683 , C12N5/0625 , C12N5/0631 , C12N5/067 , C12N5/0688 , C12N2500/05 , C12N2500/40 , C12N2501/01 , C12N2501/11 , C12N2501/33 , C12N2501/39 , C12N2501/727 , C12N2502/13 , C12N2502/1323 , C12N2503/02 , C12N2510/04 , C12Q1/6883 , C12Q2600/106 , C12Q2600/158 , G01N33/5091
摘要： The present invention is directed towards methods of culturing non-keratinocyte epithelial cells, with the methods comprising culturing non-keratinocyte epithelial cells in the presence of feeder cells and a calcium-containing medium while inhibiting the activity of Rho kinase (ROCK) in the feeder cell, the non-keratinocyte epithelial cells or both during culturing.

10. 发明授权

US08566759B2 Structure for on chip shielding structure for integrated circuits or devices on a substrate 有权
标题翻译：用于集成电路或基板上的器件的片上屏蔽结构的结构
公开(公告)号：US08566759B2
公开(公告)日：2013-10-22
申请号：US12046750
申请日：2008-03-12
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： G01R1/18 , G01R31/2851 , H01L23/552 , H01L23/66 , H01L2223/6627 , H01L2223/665 , H01L2924/0002 , H01L2924/1903 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置分别。该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

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