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1. 发明授权

US08464001B1 Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism 有权
标题翻译：缓存和相关方法与帧缓冲区管理脏数据拉和高优先级清理机制
公开(公告)号：US08464001B1
公开(公告)日：2013-06-11
申请号：US12331305
申请日：2008-12-09
申请人： John H. Edmondson , David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
发明人： John H. Edmondson , David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/0804 , G06F12/12 , G06F2212/302
摘要： Systems and methods are disclosed for managing the number of affirmatively associated cache lines related to the different sets of a data cache unit. A tag look-up unit implements two thresholds, which may be configurable thresholds, to manage the number of cache lines related to a given set that store dirty data or are reserved for in-flight read requests. If the number of affirmatively associated cache lines in a given set is equal to a maximum threshold, the tag look-up unit stalls future requests that require an available cache line within that set to be affirmatively associated. To reduce the number of stalled requests, the tag look-up unit transmits a high priority clean notification to a frame buffer logic when the number of affirmatively associated cache lines in a given set approaches the maximum threshold. The frame buffer logic then processes requests associated with that set preemptively.
摘要翻译：公开了用于管理与数据高速缓存单元的不同集合相关的肯定关联的高速缓存行的数量的系统和方法。标签查找单元实现两个阈值，其可以是可配置的阈值，以管理与存储脏数据的给定集合相关的高速缓存行的数量或者被保留用于飞行读取请求。如果给定集合中的肯定关联的高速缓存行的数量等于最大阈值，则标签查找单元停止需要在该集合内可用的高速缓存行被肯定地关联的将来的请求。为了减少停止请求的数量，当给定集中的肯定关联的高速缓存行的数量接近最大阈值时，标签查找单元向帧缓冲器逻辑发送高优先级的清除通知。帧缓冲器逻辑然后预先处理与该组相关联的请求。

2. 发明申请

US20130124802A1 Class Dependent Clean and Dirty Policy 有权
标题翻译：类依赖的清洁和肮脏的政策
公开(公告)号：US20130124802A1
公开(公告)日：2013-05-16
申请号：US13296119
申请日：2011-11-14
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
IPC分类号： G06F12/08
CPC分类号： G06F12/0804
摘要： A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
摘要翻译：公开了一种用于清除中间高速缓存中的脏数据的方法。当脏数据存储在L2高速缓存中时，包含存储器地址和数据类的脏数据通知由级别2（L2）高速缓存发送到帧缓冲器逻辑。数据类可能包括首先驱逐，最后驱逐正常和驱逐。在一个实施例中，属于第一数据类别的数据是具有很少重用潜力的光栅操作数据。帧缓冲器逻辑使用通知排序器来组织脏数据通知，其中通知分类器中的条目存储DRAM存储体页面编号，具有驻留脏数据的高速缓存行的第一计数和具有居民驱逐器的第一高速缓存行计数与该DRAM库相关联的脏数据。当第一计数达到阈值时，帧缓冲器逻辑发送与条目相关联的脏数据。

3. 发明授权

US08949541B2 Techniques for evicting dirty data from a cache using a notification sorter and count thresholds 有权
标题翻译：使用通知排序器和计数阈值从缓存中排除脏数据的技术
公开(公告)号：US08949541B2
公开(公告)日：2015-02-03
申请号：US13296119
申请日：2011-11-14
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804
摘要： A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
摘要翻译：公开了一种用于清除中间高速缓存中的脏数据的方法。当脏数据存储在L2高速缓存中时，包含存储器地址和数据类的脏数据通知由级别2（L2）高速缓存发送到帧缓冲器逻辑。数据类可能包括首先驱逐，最后驱逐正常和驱逐。在一个实施例中，属于第一数据类别的数据是具有很少重用潜力的光栅操作数据。帧缓冲器逻辑使用通知排序器来组织脏数据通知，其中通知分类器中的条目存储DRAM存储体页面编号，具有驻留脏数据的高速缓存行的第一计数和具有居民驱逐器的第一高速缓存行计数与该DRAM库相关联的脏数据。当第一计数达到阈值时，帧缓冲器逻辑发送与条目相关联的脏数据。

4. 发明授权

US08234478B1 Using a data cache array as a DRAM load/store buffer 有权
标题翻译：使用数据高速缓存阵列作为DRAM加载/存储缓冲区
公开(公告)号：US08234478B1
公开(公告)日：2012-07-31
申请号：US12256400
申请日：2008-10-22
申请人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
发明人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895
摘要： One embodiment of the invention sets forth a mechanism for using the L2 cache as a buffer for data associated with read/write commands that are processed by the frame buffer logic. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves necessary cache lines for the read/write operations and transmits read commands to the frame buffer logic for processing. A data slice scheduler transmits a dirty data notification to the frame buffer logic when data associated with a write command is stored in an SRAM bank. The data slice scheduler schedules accesses to the SRAM banks and gives priority to accesses requested by the frame buffer logic to store or retrieve data associated with read/write commands. This feature allows cache lines reserved for read/write commands that are processed by the frame buffer logic to be made available at the earliest clock cycle.
摘要翻译：本发明的一个实施例提出了一种使用L2高速缓存作为与由帧缓冲器逻辑处理的读/写命令相关联的数据的缓冲器的机制。标签查找单元跟踪L2高速缓存中每个高速缓存行的可用性，为读/写操作预留必要的高速缓存行，并将读命令发送到帧缓冲器逻辑进行处理。当与写命令相关联的数据被存储在SRAM存储体中时，数据片调度器将脏数据通知发送到帧缓冲器逻辑。数据片调度器调度对SRAM组的访问，并且优先级由帧缓冲器逻辑请求的访问来存储或检索与读/写命令相关联的数据。该功能允许由帧缓冲器逻辑处理的读/写命令保留的高速缓存行在最早的时钟周期内可用。

5. 发明授权

US08131931B1 Configurable cache occupancy policy 有权
标题翻译：可配置缓存占用策略
公开(公告)号：US08131931B1
公开(公告)日：2012-03-06
申请号：US12256378
申请日：2008-10-22
申请人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
发明人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
IPC分类号： G06F12/00
CPC分类号： G06F12/121
摘要： One embodiment of the invention is a method for evicting data from an intermediary cache that includes the steps of receiving a command from a client, determining that there is a cache miss relative to the intermediary cache, identifying one or more cache lines within the intermediary cache to store data associated with the command, determining whether any of data residing in the one or more cache lines includes raster operations data or normal data, and causing the data residing in the one or more cache lines to be evicted or stalling the command based, at least in part, on whether the data includes raster operations data or normal data. Advantageously, the method allows a series of cache eviction policies based on how cached data is categorized and the eviction classes of the data. Consequently, more optimized eviction decisions may be made, leading to fewer command stalls and improved performance.
摘要翻译：本发明的一个实施例是一种用于从中间缓存中取出数据的方法，包括以下步骤：从客户机接收命令，确定相对于中间缓存存在高速缓存未命中，识别中间缓存内的一个或多个高速缓存行存储与所述命令相关联的数据，确定驻留在所述一个或多个高速缓存行中的数据中的任何一个是否包括光栅操作数据或正常数据，以及使驻留在所述一个或多个高速缓存行中的数据被驱逐或停止所述命令，至少部分地关于数据是否包括光栅操作数据或正常数据。有利地，该方法允许基于缓存数据被分类和数据的逐出类别的一系列缓存驱逐策略。因此，可以进行更优化的驱逐决定，导致更少的命令停顿和改进的性能。

6. 发明授权

US08060700B1 System, method and frame buffer logic for evicting dirty data from a cache using counters and data types 有权
标题翻译：使用计数器和数据类型从缓存中排除脏数据的系统，方法和帧缓冲区逻辑
公开(公告)号：US08060700B1
公开(公告)日：2011-11-15
申请号：US12330469
申请日：2008-12-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
IPC分类号： G06F13/00 , G06F12/12
CPC分类号： G06F12/126 , G06F12/0804 , G06F2212/302
摘要： A system and method for cleaning dirty data in an intermediate cache are disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
摘要翻译：公开了一种用于清除中间缓存中的脏数据的系统和方法。当脏数据存储在L2高速缓存中时，包含存储器地址和数据类的脏数据通知由级别2（L2）高速缓存发送到帧缓冲器逻辑。数据类包括先驱逐出，最后逐出。在一个实施例中，属于第一数据类别的数据是具有很少重用潜力的光栅操作数据。帧缓冲器逻辑使用通知排序器来组织脏数据通知，其中通知分类器中的条目存储DRAM存储体页面编号，具有驻留脏数据的高速缓存行的第一计数和具有居民驱逐器的第一高速缓存行计数与该DRAM库相关联的脏数据。当第一个计数达到阈值时，帧缓冲器逻辑发送与条目相关联的脏数据。

7. 发明授权

US08595437B1 Compression status bit cache with deterministic isochronous latency 有权
标题翻译：具有确定性同步延迟的压缩状态位缓存
公开(公告)号：US08595437B1
公开(公告)日：2013-11-26
申请号：US12276147
申请日：2008-11-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/084 , G06F2212/302 , G06F2212/401
摘要： One embodiment of the present invention sets forth a compression status bit cache with deterministic latency for isochronous memory clients of compressed memory. The compression status bit cache improves overall memory system performance by providing on-chip availability of compression status bits that are used to size and interpret a memory access request to compressed memory. To avoid non-deterministic latency when an isochronous memory client accesses the compression status bit cache, two design features are employed. The first design feature involves bypassing any intermediate cache when the compression status bit cache reads a new cache line in response to a cache read miss, thereby eliminating additional, potentially non-deterministic latencies outside the scope of the compression status bit cache. The second design feature involves maintaining a minimum pool of clean cache lines by opportunistically writing back dirty cache lines and, optionally, temporarily blocking non-critical requests that would dirty already clean cache lines. With clean cache lines available to be overwritten quickly, the compression status bit cache avoids incurring additional miss write back latencies.
摘要翻译：本发明的一个实施例针对压缩存储器的同步存储器客户端提出了具有确定性延迟的压缩状态位缓存。压缩状态位缓存通过提供压缩状态位的片上可用性来提高整体存储器系统性能，压缩状态位用于对存储器访问请求进行大小和解释，并将其解释为压缩存储器。为了避免同步存储器客户端访问压缩状态位缓存时的非确定性延迟，采用了两个设计特征。第一个设计功能涉及当压缩状态位缓存读取新的高速缓存行以响应高速缓存读取未命中时绕过任何中间缓存，从而消除在压缩状态位缓存范围之外的额外的潜在的非确定性延迟。第二个设计功能包括通过机会地写回脏的高速缓存线，以及可选地临时阻止将已经清除高速缓存行的非关键请求，来保持最小的干净的高速缓存行池。使用干净的缓存线可以快速覆盖，压缩状态位缓存避免了额外的错误回写延迟。

8. 发明授权

US08108610B1 Cache-based control of atomic operations in conjunction with an external ALU block 有权
标题翻译：结合外部ALU块的基于缓存的原子操作控制
公开(公告)号：US08108610B1
公开(公告)日：2012-01-31
申请号：US12255595
申请日：2008-10-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/16
CPC分类号： G06F12/084 , G06F12/08 , G06F12/0815 , G06F15/8015 , G06F2212/251 , G06F2212/253 , G06T1/20
摘要： One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the necessary cache lines for the atomic operations and transmits the atomic operations to an ALU for processing. The tag look-up unit also increments a reference counter associated with a reserved cache line each time an atomic operation associated with that cache line is received. This feature allows multiple atomic operations associated with the same cache line to be pipelined to the ALU. A ROP unit that includes the ALU may request additional data necessary to process an atomic operation from the L2 cache. Result data is stored in the L2 cache and may also be returned to the general processing clusters.
摘要翻译：本发明的一个实施例提出了一种用于有效地处理从多个通用处理群集发送到L2高速缓存的原子操作的机制。标签查找单元跟踪L2高速缓存中每个高速缓存行的可用性，为原子操作预留必要的高速缓存行，并将原子操作发送到ALU进行处理。每当与该高速缓存行相关联的原子操作被接收时，标签查找单元也增加与保留高速缓存行相关联的参考计数器。此功能允许将与同一高速缓存线相关联的多个原子操作流水线连接到ALU。包括ALU的ROP单元可以请求从L2高速缓存处理原子操作所需的附加数据。结果数据存储在L2缓存中，也可以返回到通用处理集群。

9. 发明授权

US08099650B1 L2 ECC implementation 有权
公开(公告)号：US08099650B1
公开(公告)日：2012-01-17
申请号：US12202160
申请日：2008-08-29
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F11/10
CPC分类号： G06F11/1064
摘要： One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.

10. 发明授权

US08156404B1 L2 ECC implementation 有权
标题翻译： L2 ECC实现
公开(公告)号：US08156404B1
公开(公告)日：2012-04-10
申请号：US12202161
申请日：2008-08-29
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.
摘要翻译：本发明的一个实施例提出了一种用于在片上L2高速缓存中实现ECC保护的方法。当数据被写入或从外部存储器读取时，L2高速缓存中的逻辑被配置为生成ECC校验位，并且将ECC校验位存储在通常被分配用于存储字节使能的空间中的L2高速缓存中。结果，可以保护存储在L2高速缓存中的数据免于位错误，而不会产生为ECC校验位提供附加存储或复杂硬件的成本。

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