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1. 发明授权

US08156404B1 L2 ECC implementation 有权
标题翻译： L2 ECC实现
公开(公告)号：US08156404B1
公开(公告)日：2012-04-10
申请号：US12202161
申请日：2008-08-29
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.
摘要翻译：本发明的一个实施例提出了一种用于在片上L2高速缓存中实现ECC保护的方法。当数据被写入或从外部存储器读取时，L2高速缓存中的逻辑被配置为生成ECC校验位，并且将ECC校验位存储在通常被分配用于存储字节使能的空间中的L2高速缓存中。结果，可以保护存储在L2高速缓存中的数据免于位错误，而不会产生为ECC校验位提供附加存储或复杂硬件的成本。

2. 发明授权

US08862823B1 Compression status caching 有权
标题翻译：压缩状态缓存
公开(公告)号：US08862823B1
公开(公告)日：2014-10-14
申请号：US12340503
申请日：2008-12-19
申请人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
发明人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/0848 , G06F12/1009 , G06F12/123 , G06F2212/1041 , G06F2212/401 , G06F2212/455 , G06F2212/466 , G06T1/60
摘要： One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.
摘要翻译：本发明的一个实施例提出了一种被配置为存储存储在外部存储器中的存储器块的压缩信息的压缩状态缓存。数据高速缓存单元被配置为基于存储在压缩状态位高速缓存中的压缩信息，响应于高速缓存未命中来请求来自外部存储器的压缩数据。活动缓冲区的压缩状态根据需要动态交换到压缩状态缓存。可以为活动缓冲区内的一个或多个瓦片指定不同的压缩格式。所公开的压缩状态高速缓存的一个优点是可以将大量附加存储器分配为可压缩存储器块，而不会引起相应的管芯区域成本，因为存储在附加存储器中的芯片外的存储器的一部分被缓存在压缩状态缓存。

3. 发明授权

US08271734B1 Method and system for converting data formats using a shared cache coupled between clients and an external memory 有权
标题翻译：使用在客户机和外部存储器之间耦合的共享缓存来转换数据格式的方法和系统
公开(公告)号：US08271734B1
公开(公告)日：2012-09-18
申请号：US12329345
申请日：2008-12-05
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F2212/401
摘要： A system and method for converting data from one format to another in a processing pipeline architecture. Data is stored in a shared cache that is coupled between one or more clients and an external memory. The shared cache provides storage that is used by multiple clients rather than being dedicated to separately convert the data format for each client. Each client may interface with the memory using a different format, such as a compressed data format. Data is converted to the format expected by the particular client as it is read from the cache and output to the client during a read operation. Bytes of a cache line may be remapped to bytes of an unpack register for output to a naïve client, which may be configured to perform texture mapping operations. Data is converted from the client format to the memory format as it is stored into the cache during a write operation.
摘要翻译：一种用于在处理流水线架构中将数据从一种格式转换为另一种格式的系统和方法。数据存储在耦合在一个或多个客户端和外部存储器之间的共享高速缓存中。共享缓存提供由多个客户端使用的存储，而不是专用于分别转换每个客户端的数据格式。每个客户端可以使用不同的格式（例如压缩数据格式）与存储器接口。在读取操作期间，数据将从特定客户端转换为预期的格式，并从缓存中读取并输出到客户端。高速缓存行的字节可以重新映射到解包寄存器的字节，以输出到初始客户机，其可以被配置为执行纹理映射操作。数据从客户端格式转换为存储格式，因为它在写操作期间存储到高速缓存中。

4. 发明授权

US08595437B1 Compression status bit cache with deterministic isochronous latency 有权
标题翻译：具有确定性同步延迟的压缩状态位缓存
公开(公告)号：US08595437B1
公开(公告)日：2013-11-26
申请号：US12276147
申请日：2008-11-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/084 , G06F2212/302 , G06F2212/401
摘要： One embodiment of the present invention sets forth a compression status bit cache with deterministic latency for isochronous memory clients of compressed memory. The compression status bit cache improves overall memory system performance by providing on-chip availability of compression status bits that are used to size and interpret a memory access request to compressed memory. To avoid non-deterministic latency when an isochronous memory client accesses the compression status bit cache, two design features are employed. The first design feature involves bypassing any intermediate cache when the compression status bit cache reads a new cache line in response to a cache read miss, thereby eliminating additional, potentially non-deterministic latencies outside the scope of the compression status bit cache. The second design feature involves maintaining a minimum pool of clean cache lines by opportunistically writing back dirty cache lines and, optionally, temporarily blocking non-critical requests that would dirty already clean cache lines. With clean cache lines available to be overwritten quickly, the compression status bit cache avoids incurring additional miss write back latencies.
摘要翻译：本发明的一个实施例针对压缩存储器的同步存储器客户端提出了具有确定性延迟的压缩状态位缓存。压缩状态位缓存通过提供压缩状态位的片上可用性来提高整体存储器系统性能，压缩状态位用于对存储器访问请求进行大小和解释，并将其解释为压缩存储器。为了避免同步存储器客户端访问压缩状态位缓存时的非确定性延迟，采用了两个设计特征。第一个设计功能涉及当压缩状态位缓存读取新的高速缓存行以响应高速缓存读取未命中时绕过任何中间缓存，从而消除在压缩状态位缓存范围之外的额外的潜在的非确定性延迟。第二个设计功能包括通过机会地写回脏的高速缓存线，以及可选地临时阻止将已经清除高速缓存行的非关键请求，来保持最小的干净的高速缓存行池。使用干净的缓存线可以快速覆盖，压缩状态位缓存避免了额外的错误回写延迟。

5. 发明授权

US08108610B1 Cache-based control of atomic operations in conjunction with an external ALU block 有权
标题翻译：结合外部ALU块的基于缓存的原子操作控制
公开(公告)号：US08108610B1
公开(公告)日：2012-01-31
申请号：US12255595
申请日：2008-10-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/16
CPC分类号： G06F12/084 , G06F12/08 , G06F12/0815 , G06F15/8015 , G06F2212/251 , G06F2212/253 , G06T1/20
摘要： One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the necessary cache lines for the atomic operations and transmits the atomic operations to an ALU for processing. The tag look-up unit also increments a reference counter associated with a reserved cache line each time an atomic operation associated with that cache line is received. This feature allows multiple atomic operations associated with the same cache line to be pipelined to the ALU. A ROP unit that includes the ALU may request additional data necessary to process an atomic operation from the L2 cache. Result data is stored in the L2 cache and may also be returned to the general processing clusters.
摘要翻译：本发明的一个实施例提出了一种用于有效地处理从多个通用处理群集发送到L2高速缓存的原子操作的机制。标签查找单元跟踪L2高速缓存中每个高速缓存行的可用性，为原子操作预留必要的高速缓存行，并将原子操作发送到ALU进行处理。每当与该高速缓存行相关联的原子操作被接收时，标签查找单元也增加与保留高速缓存行相关联的参考计数器。此功能允许将与同一高速缓存线相关联的多个原子操作流水线连接到ALU。包括ALU的ROP单元可以请求从L2高速缓存处理原子操作所需的附加数据。结果数据存储在L2缓存中，也可以返回到通用处理集群。

6. 发明授权

US08099650B1 L2 ECC implementation 有权
公开(公告)号：US08099650B1
公开(公告)日：2012-01-17
申请号：US12202160
申请日：2008-08-29
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F11/10
CPC分类号： G06F11/1064
摘要： One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.

7. 发明授权

US08700862B2 Compression status bit cache and backing store 有权
标题翻译：压缩状态位缓存和后备存储
公开(公告)号：US08700862B2
公开(公告)日：2014-04-15
申请号：US12327790
申请日：2008-12-03
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/08 , G06F12/0875 , G06F12/128 , G06F2212/1024 , G06F2212/401
摘要： A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.
摘要翻译：压缩状态位缓存提供压缩状态位的片上可用性，用于确定需要多少位以访问潜在的压缩的存储器块。驻留在附加存储器的保留区域中的备份存储器为用于表示驻留在附加存储器中的任意大量块的压缩状态的一整套压缩状态位提供存储。用于在多个物理存储器设备上分配存储器访问模式的物理地址重映射（“swizzling”）被压缩状态位高速缓存部分地复制，以有效地整合后备存储数据与其他用户数据的分配和访问。

8. 发明授权

US08627041B2 Efficient line and page organization for compression status bit caching 有权
标题翻译：用于压缩状态位缓存的高效线和页组织
公开(公告)号：US08627041B2
公开(公告)日：2014-01-07
申请号：US12901452
申请日：2010-10-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/08 , G06F12/0875 , G06F12/1009 , G06F2212/401
摘要： One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.
摘要翻译：本发明的一个实施例提出了一种对包括任意数量的分区的虚拟映射的存储器系统中的压缩数据执行存储器访问请求的技术。虚拟地址被映射到由页表项（PTE）指定的线性物理地址。 PTE被配置为存储压缩属性，其用于定位压缩状态位缓存内的对应物理存储器页的压缩状态。压缩状态位缓存与压缩状态位后备存储一起操作。如果从压缩状态位缓存获得压缩状态，则存储器访问请求使用压缩状态进行。如果压缩状态位缓存未命中，则错误触发后备存储器的填充操作。填充完成后，使用新填充的压缩状态信息进行内存访问。

9. 发明授权

US08135926B1 Cache-based control of atomic operations in conjunction with an external ALU block 有权
公开(公告)号：US08135926B1
公开(公告)日：2012-03-13
申请号：US12255599
申请日：2008-10-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/02
CPC分类号： G06F12/084 , G06F9/3851 , G06F9/3881 , G06F12/0806
摘要： One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the necessary cache lines for the atomic operations and transmits the atomic operations to an ALU for processing. The tag look-up unit also increments a reference counter associated with a reserved cache line each time an atomic operation associated with that cache line is received. This feature allows multiple atomic operations associated with the same cache line to be pipelined to the ALU. A ROP unit that includes the ALU may request additional data necessary to process an atomic operation from the L2 cache. Result data is stored in the L2 cache and may also be returned to the general processing clusters.

10. 发明申请

US20100138614A1 Compression Status Bit Cache And Backing Store 有权
标题翻译：压缩状态位缓存和备份存储
公开(公告)号：US20100138614A1
公开(公告)日：2010-06-03
申请号：US12327790
申请日：2008-12-03
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/08 , G06F12/0875 , G06F12/128 , G06F2212/1024 , G06F2212/401
摘要： One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.
摘要翻译：本发明的一个实施例提出了一种用于在附加到数据处理芯片的存储器的压缩块内增加可用存储空间的技术，而不需要片上压缩状态位的比例增加。压缩状态位缓存提供压缩状态位的片上可用性，用于确定需要多少位以访问潜在的压缩的存储器块。驻留在附加存储器的保留区域中的备份存储器为用于表示驻留在附加存储器中的任意大量块的压缩状态的一整套压缩状态位提供存储。用于在多个物理存储器设备上分配存储器访问模式的物理地址重映射（“swizzling”）被压缩状态位高速缓存部分地复制，以有效地整合后备存储数据与其他用户数据的分配和访问。

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