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1. 发明申请

US20060179238A1 Store stream prefetching in a microprocessor 失效
标题翻译：在微处理器中存储流预取
公开(公告)号：US20060179238A1
公开(公告)日：2006-08-10
申请号：US11054871
申请日：2005-02-10
申请人： John Griswell , Hung Le , Francis O'Connell , William Starke , Jeffrey Stuecheli , Albert Williams
发明人： John Griswell , Hung Le , Francis O'Connell , William Starke , Jeffrey Stuecheli , Albert Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/30047 , G06F9/383 , G06F12/0811
摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.
摘要翻译：在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

2. 发明申请

US20080028155A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COHERENCY COMMUNICATION UTILIZING COHERENCY DOMAIN INDICATORS 有权
标题翻译：数据处理系统和方法，用于有效的通信使用相关域指标
公开(公告)号：US20080028155A1
公开(公告)日：2008-01-31
申请号：US11835259
申请日：2007-08-07
申请人： JAMES FIELDS , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： JAMES FIELDS , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

3. 发明申请

US20070168639A1 Data processing system and method for selecting a scope of broadcast of an operation by reference to a translation table 审中-公开
标题翻译：参考翻译表选择操作的广播范围的数据处理系统和方法
公开(公告)号：US20070168639A1
公开(公告)日：2007-07-19
申请号：US11333607
申请日：2006-01-17
申请人： John McCalpin , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： John McCalpin , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0833 , G06F12/10 , G06F2212/507
摘要： A data processing system includes at least first and second coherency domains coupled by an interconnect fabric. A memory coupled to the interconnect fabric includes an address translation table having a translation table entry utilized to translate virtual memory addresses to real memory addresses. The translation table entry also includes scope information for broadcast operations targeting addresses within a memory region associated with the translation table entry. Scope prediction logic within the first coherency domain predictively selects a scope of broadcast of an operation on an interconnect fabric of the data processing system by reference to the scope information within the address translation table entry.
摘要翻译：数据处理系统至少包括由互连结构耦合的第一和第二相干域。耦合到互连结构的存储器包括具有用于将虚拟存储器地址转换为实际存储器地址的转换表项的地址转换表。转换表条目还包括针对与转换表条目相关联的存储器区域内的地址的广播操作的范围信息。第一相干域内的范围预测逻辑通过参考地址转换表条目中的范围信息预测性地选择数据处理系统的互连结构上的操作的广播范围。

4. 发明申请

US20070073919A1 Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes 失效
标题翻译：允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法
公开(公告)号：US20070073919A1
公开(公告)日：2007-03-29
申请号：US11226967
申请日：2005-09-15
申请人： George Daly , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： George Daly , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.
摘要翻译：数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控制器的第二处理。存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点与第二个地址关联的域指示符。

5. 发明申请

US20060224833A1 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state 有权
公开(公告)号：US20060224833A1
公开(公告)日：2006-10-05
申请号：US11095734
申请日：2005-03-31
申请人： Guy Guthrie , Aaron Sawdey , William Starke , Jeffrey Stuecheli
发明人： Guy Guthrie , Aaron Sawdey , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.

6. 发明申请

US20060179249A1 Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory 有权
标题翻译：数据处理系统和方法，用于使用存储器的位置预测性地选择操作的广播范围
公开(公告)号：US20060179249A1
公开(公告)日：2006-08-10
申请号：US11055697
申请日：2005-02-10
申请人： James Fields , Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Phillip Williams
发明人： James Fields , Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Phillip Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译：高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

7. 发明申请

US20080052471A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IG COHERENCY STATE 失效
标题翻译：数据处理系统和使用IG语音状态的高效通信的方法
公开(公告)号：US20080052471A1
公开(公告)日：2008-02-28
申请号：US11836965
申请日：2007-08-10
申请人： JAMES FIELDS, JR. , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： JAMES FIELDS, JR. , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

8. 发明申请

US20080016284A1 DATA PROCESSING SYSTEM AND METHOD FOR PREDICTIVELY SELECTING A SCOPE OF BROADCAST OF AN OPERATION UTILIZING A HISTORY-BASED PREDICTION 审中-公开
标题翻译：数据处理系统和方法，用于预测性地选择使用基于历史的预测操作的广播范围
公开(公告)号：US20080016284A1
公开(公告)日：2008-01-17
申请号：US11863979
申请日：2007-09-28
申请人： BENJIMAN GOODMAN , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： BENJIMAN GOODMAN , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译：根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。通过参考预测器预测性地选择后续操作的广播范围。

9. 发明申请

US20060179247A1 Data processing system and method for efficient communication utilizing an Ig coherency state 失效
公开(公告)号：US20060179247A1
公开(公告)日：2006-08-10
申请号：US11055524
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.

10. 发明申请

US20060179234A1 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US20060179234A1
公开(公告)日：2006-08-10
申请号：US11054390
申请日：2005-02-09
申请人： Robert Bell , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Robert Bell , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。

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