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1. 发明申请

US20060224833A1 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state 有权
公开(公告)号：US20060224833A1
公开(公告)日：2006-10-05
申请号：US11095734
申请日：2005-03-31
申请人： Guy Guthrie , Aaron Sawdey , William Starke , Jeffrey Stuecheli
发明人： Guy Guthrie , Aaron Sawdey , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.

2. 发明申请

US20060236037A1 Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source 有权
标题翻译：高速缓冲存储器，处理单元，数据处理系统和方法，用于基于请求源假设所选择的无效一致性状态
公开(公告)号：US20060236037A1
公开(公告)日：2006-10-19
申请号：US11109085
申请日：2005-04-19
申请人： Guy Guthrie , Aaron Sawdey , William Starke , Derek Williams
发明人： Guy Guthrie , Aaron Sawdey , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0831
摘要： At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. In response to receipt of the exclusive memory access operation, the first cache memory detects presence or absence of a source indication indicating that the exclusive memory access operation originated from the second cache memory to which the first cache memory is coupled by a private communication network to which the third cache memory is not coupled. In response to detecting presence of the source indication, a coherency state field of the first cache memory that is associated with the target address is updated to a first data-invalid state. In response to detecting absence of the source indication, the coherency state field of the first cache memory is updated to a different second data-invalid state.
摘要翻译：在与第一处理器核心相关联的第一高速缓冲存储器处，通过将第一高速缓冲存储器耦合到分别隶属于第二和第三处理器核的第二和第三高速缓冲存储器的互连结构接收独占存储器存取操作。独占内存访问操作指定目标地址。响应于独占存储器访问操作的接收，第一高速缓存存储器检测是否存在指示来自第一高速缓存存储器的专用存储器访问操作的源指示由第一高速缓冲存储器通过专用通信网络耦合到第三缓存存储器未被耦合。响应于检测到源指示的存在，与目标地址相关联的第一高速缓冲存储器的一致性状态字段被更新为第一数据无效状态。响应于检测到不存在源指示，将第一高速缓冲存储器的一致性状态字段更新为不同的第二数据无效状态。

3. 发明申请

US20050125592A1 Multi-level cache having overlapping congruence groups of associativity sets in different cache levels 有权
标题翻译：具有不同高速缓存级别的关联性集合的重叠同余组的多级缓存
公开(公告)号：US20050125592A1
公开(公告)日：2005-06-09
申请号：US10731065
申请日：2003-12-09
申请人： Aaron Sawdey
发明人： Aaron Sawdey
IPC分类号： G06F12/08 , G06F12/00 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0864 , G06F12/127
摘要： A computer cache memory having at least two levels includes associativity sets allocated to congruence groups, each congruence group having multiple associativity sets (preferably two) in the higher level cache and multiple associativity sets (preferably three) in the lower level cache. The address range of an associativity set in the higher level cache is distributed among all the associativity sets in the lower level cache within the same congruence group, so that these lower level associativity sets are effectively shared by all associativity sets in the same congruence group in the higher level. The lower level cache is preferably a victim cache of the higher level cache. This sharing of lower level associativity sets by different associativity sets in the higher level effectively increases the associativity of the lower level to hold cast-outs of a hot associativity set in the upper level.
摘要翻译：具有至少两个级别的计算机高速缓冲存储器包括分配给同余组的关联性集合，每个等同组具有较高级别高速缓存中的多个关联集合（优选为两个），以及较低级别高速缓存中的多个关联集合（优选三个）。在较高级别高速缓存中设置的关联性的地址范围被分配在同一同余组中的较低级高速缓存中的所有关联集合中，使得这些较低级别的关联性集合被相同同余组中的所有关联集合有效共享更高层次。较低级缓存优选地是较高级缓存的受害缓存。较高级别的不同关联集合的较低层次关联集合的共享有效地提高了较低级别的关联性，从而保持了较高级别的热关联集合的转移。

4. 发明申请

US20060106991A1 Victim prefetching in a cache hierarchy 失效
标题翻译：受害者在缓存层次结构中预取
公开(公告)号：US20060106991A1
公开(公告)日：2006-05-18
申请号：US10989997
申请日：2004-11-16
申请人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
发明人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
IPC分类号： G06F12/00
CPC分类号： G06F12/122 , G06F12/0862 , G06F12/0897
摘要： We present a “directory extension” (hereinafter “DX”) to aid in prefetching between proximate levels in a cache hierarchy. The DX may maintain (1) a list of pages which contains recently ejected lines from a given level in the cache hierarchy, and (2) for each page in this list, the identity of a set of ejected lines, provided these lines are prefetchable from, for example, the next level of the cache hierarchy. Given a cache fault to a line within a page in this list, other lines from this page may then be prefetched without the substantial overhead to directory lookup which would otherwise be required.
摘要翻译：我们提出一个“目录扩展名”（以下简称“DX”）来辅助缓存层级中的邻近级别之间的预取。 DX可以维护（1）包含最近从缓存层级中的给定级别排出的行的页面列表，以及（2）对于该列表中的每个页面，提供这些行是可预取的集合的标识从例如缓存层次结构的下一级。给定列表中页面内的行的高速缓存错误，然后可以预取此页面中的其他行，而不需要大量开销，否则将需要目录查找。

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