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1. 发明授权

US5881261A Processing system that rapidly indentifies first or second operations of selected types for execution 失效
标题翻译：快速确定所选类型的第一或第二操作执行的处理系统
公开(公告)号：US5881261A
公开(公告)日：1999-03-09
申请号：US650055
申请日：1996-05-16
申请人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
发明人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
IPC分类号： G06F7/74 , G06F9/38 , G06F9/30
CPC分类号： G06F7/74 , G06F9/30094 , G06F9/30174 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3873 , G06F9/3889
摘要： A processing system includes sequential entries for storing operations of different types and a scan chain which can identify an operation of a first type which follows after an operation of a second type. The first and second types can be identical so that the scan chain identifies the second operation of a particular type in the sequence. The scan chain includes single-entry "generate", "propagate", "kill", and "only" terms which control a scan bit. Conceptually, if the "only" term is not asserted, an entry of the second type generates the scan bit and asserts the "only" term. After the "only" term is asserted, further generation of the scan bit is inhibited. Each entry either propagates the scan bit to the next entry or if the entry is of the first type, kills the scan bit and identifies itself as the selected entry. Look-ahead logic determines group terms from single-entry terms to indicate whether a scan bit would be generated, propagated, or killed by a group of entries. Accordingly, the scan bit is not required to propagate through every entry, and scans can be performed quickly.
摘要翻译：处理系统包括用于存储不同类型的操作的顺序条目和可识别第二类操作之后的第一类型的操作的扫描链。第一和第二类型可以相同，使得扫描链标识序列中特定类型的第二操作。扫描链包括控制扫描位的单个条目“生成”，“传播”，“杀死”和“唯一”术语。在概念上，如果“唯一”术语没有被断言，则第二种类型的条目生成扫描位并且断言“唯一”项。在“唯一”术语被断言之后，进一步产生扫描位被禁止。每个条目将扫描位传播到下一个条目，或者如果条目是第一个条目，则将扫描位置并将其标识为所选条目。先行逻辑从单项条目确定组术语，以指示扫描位是否由一组条目生成，传播或杀死。因此，扫描位不需要通过每个条目传播，并且可以快速执行扫描。

2. 发明授权

US5745724A Scan chain for rapidly identifying first or second objects of selected types in a sequential list 失效
标题翻译：扫描链，用于在顺序列表中快速识别所选类型的第一或第二对象
公开(公告)号：US5745724A
公开(公告)日：1998-04-28
申请号：US592722
申请日：1996-01-26
申请人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
发明人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
IPC分类号： G06F7/74 , G06F9/38 , G06F9/30
CPC分类号： G06F7/74 , G06F9/30094 , G06F9/30174 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3873 , G06F9/3889
摘要： A circuit includes a sequential entries for storing objects of different types and a scan chain which can identify an object of a first type which follows after an object of a second type. The first and second types can be identical so that the scan chain identifies the second object of a particular type in the sequence. The scan chain includes single-entry "generate", "propagate", "kill", and "only" terms which control a scan bit. Conceptually, if the "only" term is not asserted, an entry of the second type generates the scan bit and asserts the "only" term. After the "only" term is asserted, further generation of the scan bit is inhibited. Each entry either propagates the scan bit to the next entry or if the entry is of the first type, kills the scan bit and identifies itself as the selected entry. Look-ahead logic determines group terms from single-entry terms to indicate whether a scan bit would be generated, propagated, or killed by a group of entries. Accordingly, the scan bit is not required to propagate through every entry, and scans can be performed quickly.
摘要翻译：电路包括用于存储不同类型的对象的顺序条目和可识别在第二类型的对象之后的第一类型的对象的扫描链。第一和第二类型可以相同，使得扫描链标识序列中特定类型的第二对象。扫描链包括控制扫描位的单个条目“生成”，“传播”，“杀死”和“唯一”术语。在概念上，如果“唯一”术语没有被断言，则第二种类型的条目生成扫描位并且断言“唯一”项。在“唯一”术语被断言之后，进一步产生扫描位被禁止。每个条目将扫描位传播到下一个条目，或者如果条目是第一个条目，则将扫描位置并将其标识为所选条目。先行逻辑从单项条目确定组术语，以指示扫描位是否由一组条目生成，传播或杀死。因此，扫描位不需要通过每个条目传播，并且可以快速执行扫描。

3. 发明授权

US6038657A Scan chains for out-of-order load/store execution control 失效
标题翻译：扫描链用于无序加载/存储执行控制
公开(公告)号：US6038657A
公开(公告)日：2000-03-14
申请号：US40087
申请日：1998-03-17
申请人： John G. Favor , Amos Ben-Meir , Warren G. Stapleton , Jeffrey E. Trull , Mark E. Roberts
发明人： John G. Favor , Amos Ben-Meir , Warren G. Stapleton , Jeffrey E. Trull , Mark E. Roberts
IPC分类号： G06F7/74 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455 , G06F9/48 , G06F9/312
CPC分类号： G06F7/74 , G06F9/30152 , G06F9/30174 , G06F9/3812 , G06F9/3816 , G06F9/382 , G06F9/3822 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/4812
摘要： Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies. In a processor having a load unit and a store unit, a load/store execution control system allows load and store instructions to execute generally out-of-order with respect to each other while enforcing data dependencies between the load and store instructions.
摘要翻译：跟踪相对于特定负载（或相对于特定商店的负载）的商店的相对年龄的扫描逻辑允许处理器容纳较年轻的商店，直到完成较旧的负载（或保持较年轻的负载，直到完成较旧的商店）。根据本发明构造的传播杀手样式前瞻扫描逻辑或树结构的，分级组织的扫描逻辑的实施例提供了较旧的存储，并且加载具有非常少的门延迟的较旧指示，即使在适于同时评估大量的处理器实施例中的操作。与扫描逻辑一起运行，地址匹配逻辑允许处理器更精确地定制其避免加载存储（或存储加载）依赖性。在具有加载单元和存储单元的处理器中，加载/存储执行控制系统允许加载和存储指令在执行加载和存储指令之间的数据依赖性的同时相对于彼此执行一般无序。

4. 发明授权

US5754812A Out-of-order load/store execution control 失效
标题翻译：无序加载/存储执行控制
公开(公告)号：US5754812A
公开(公告)日：1998-05-19
申请号：US592209
申请日：1996-01-26
申请人： John G. Favor , Amos Ben-Meir , Warren G. Stapleton , Jeffrey E. Trull , Mark E. Roberts
发明人： John G. Favor , Amos Ben-Meir , Warren G. Stapleton , Jeffrey E. Trull , Mark E. Roberts
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/312
CPC分类号： G06F9/30149 , G06F9/30174 , G06F9/3812 , G06F9/3834 , G06F9/3838 , G06F9/3853
摘要： Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Propagate-kill scan chains supply the relative age indications of loads with respect to stores (and of stores with respect to loads).
摘要翻译：跟踪相对于特定负载（以及相对于特定商店的负载）的商店的相对年龄的调度器逻辑允许根据本发明构建的加载存储执行控制器保存较年轻的存储，直到完成较旧的负载（并持有年轻的货物，直到完成旧店）。地址匹配逻辑允许根据本发明构造的加载存储执行控制器避免加载存储（和存储加载）依赖性。传播杀手扫描链提供相对于商店（以及相对于负载的商店）的负载的相对年龄指示。

5. 发明授权

US06405305B1 Rapid execution of floating point load control word instructions 有权
标题翻译：快速执行浮点负载控制字指令
公开(公告)号：US06405305B1
公开(公告)日：2002-06-11
申请号：US09394024
申请日：1999-09-10
申请人： Stephan G. Meier , Jeffrey E. Trull , Derrick R. Meyer , Norbert Juffa
发明人： Stephan G. Meier , Jeffrey E. Trull , Derrick R. Meyer , Norbert Juffa
IPC分类号： G06F9302
CPC分类号： G06F9/30087 , G06F9/30043 , G06F9/30094 , G06F9/30101 , G06F9/30189 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.
摘要翻译：具有浮点单元的微处理器被配置为在程序顺序上下文中快速执行浮点负载控制字（FLDCW）类型指令。浮点单元被配置为在调度FLDCW类型指令之前调度比FLDCW类型指令更早的指令。 FLDCW型指令作为屏障，以防止在FLDCW类型指令之前执行FLDCW类型指令之后的程序顺序发生的指令。指示符位可以用于简化指令调度，并且可以存储具有长执行周期的指令的浮点控制字的副本。还公开了一种配置成在程序顺序上下文中快速执行FLDCW型指令的方法和计算机。

6. 发明授权

US06247114B1 Rapid selection of oldest eligible entry in a queue 有权
标题翻译：快速选择队列中最旧的合格条目
公开(公告)号：US06247114B1
公开(公告)日：2001-06-12
申请号：US09253478
申请日：1999-02-19
申请人： Jeffrey E. Trull
发明人： Jeffrey E. Trull
IPC分类号： G06F930
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A microprocessor having an instruction queue capable of out-of-order instruction dispatch and rapidly selecting one or more oldest eligible entries is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. The control logic may comprise a number of pluralities of multiplexers, wherein the first plurality of multiplexers are configured to select a first subset of the instructions stored in the queue. The second plurality of multiplexers then select a second subset of instructions from the first subset. This process is repeated in each successive plurality of multiplexers until the oldest eligible entry is selected. A data queue and method for managing a queue are also contemplated, as is a computer system utilizing the above-mentioned microprocessor.
摘要翻译：公开了一种具有能够无序指令分派并且快速选择一个或多个最旧的合格条目的指令队列的微处理器。微处理器可以包括多个指令执行流水线，指令高速缓存和连接到指令高速缓存和执行流水线的指令队列。指令队列可以包括多个指令存储位置，并且可以被配置为在每个时钟周期输出高达预定数量的非顺序的乱序指令。微处理器可进一步配置有与指令队列相连的高速控制逻辑。控制逻辑可以包括多个多路复用器，其中第一多个复用器被配置为选择存储在队列中的指令的第一子集。然后，第二多路复用器从第一子集中选择第二指令子集。在每个连续的多个复用器中重复该过程，直到选择最旧的合格条目。也可以考虑用于管理队列的数据队列和方法，以及利用上述微处理器的计算机系统。

7. 发明授权

US5497477A System and method for replacing a data entry in a cache memory 失效
标题翻译：用于替换高速缓冲存储器中的数据条目的系统和方法
公开(公告)号：US5497477A
公开(公告)日：1996-03-05
申请号：US206245
申请日：1994-03-07
申请人： Jeffrey E. Trull
发明人： Jeffrey E. Trull
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/124 , G06F12/1027
摘要： A method and apparatus called a cache insertion selector for selecting a slot of a memory cache in which to insert data. The access history of a slot is monitored with a single boolean variable called "used recently". A slot is marked as "used recently" when it is accessed. When a new entry is to be inserted, the cache insertion selector of the present invention attempts to select a slot which is not marked as "used recently". If all slots are marked as used recently, the cache insertion selector marks all slots as not used recently and selects one slot. A slot can be specified for unconditional selection. Also, a slot can be precluded from being selected.
摘要翻译：一种称为高速缓存插入选择器的方法和装置，用于选择其中插入数据的存储器高速缓存的时隙。使用一个名为“最近使用”的布尔变量监视插槽的访问历史。一个插槽在被访问时被标记为“最近使用”。当要插入新条目时，本发明的高速缓存插入选择器尝试选择未被标记为“最近使用”的时隙。如果所有插槽被标记为最近使用，高速缓存插入选择器将所有插槽标记为最近不使用，并选择一个插槽。可以指定一个插槽以进行无条件选择。此外，可以排除插槽。

8. 发明授权

US06460130B1 Detecting full conditions in a queue 有权
标题翻译：检测队列中的全部条件
公开(公告)号：US06460130B1
公开(公告)日：2002-10-01
申请号：US09281079
申请日：1999-03-30
申请人： Jeffrey E. Trull , Eric W. Mahurin
发明人： Jeffrey E. Trull , Eric W. Mahurin
IPC分类号： G06F1300
CPC分类号： G06F9/3816 , G06F9/30152 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A microprocessor having an instruction queue capable of out-of-order instruction dispatch and efficiently detect full conditions is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. Instead of determining exactly how many empty storage locations are present in the queue, the control logic may be configured to determine whether the number of non-overlapping strings of empty storage locations is greater than or equal to the number of estimated instructions currently on their way to being stored in the instruction queue. A data queue and method for managing a queue are also disclosed, as is a computer system utilizing the above-mentioned microprocessor.
摘要翻译：公开了一种具有能够无序指令分派并有效地检测完整条件的指令队列的微处理器。微处理器可以包括多个指令执行流水线，指令高速缓存和连接到指令高速缓存和执行流水线的指令队列。指令队列可以包括多个指令存储位置，并且可以被配置为在每个时钟周期输出高达预定数量的非顺序的乱序指令。微处理器可进一步配置有与指令队列相连的高速控制逻辑。准确地确定队列中存在多少空的存储位置，而不是确定控制逻辑可以被配置为确定空的存储位置的非重叠字符串的数量是否大于或等于当前在其路上的估计指令的数量存储在指令队列中。还公开了一种用于管理队列的数据队列和方法，以及利用上述微处理器的计算机系统。

9. 发明授权

US07188325B1 Method for selecting transistor threshold voltages in an integrated circuit 有权
标题翻译：在集成电路中选择晶体管阈值电压的方法
公开(公告)号：US07188325B1
公开(公告)日：2007-03-06
申请号：US10957848
申请日：2004-10-04
申请人： Marius Evers , Jeffrey E. Trull , Alper Halbutogullari , Robert W. Williams
发明人： Marius Evers , Jeffrey E. Trull , Alper Halbutogullari , Robert W. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045
摘要： In one embodiment, a method for selecting transistor threshold voltages on an integrated circuit may include assigning a first threshold voltage to selected groups of transistors such as cell instances, for example, and determining which of the selected groups of transistors to assign a second threshold voltage, that is lower than the first threshold voltage, by iteratively performing a cost/benefit analysis. The method may further include determining which of the selected groups of transistors having a third threshold voltage to assign the first threshold voltage by iteratively performing a cost/benefit analysis. The cost/benefit analysis may include calculating a cost/benefit ratio for each group of the selected groups of transistors. In addition, the cost/benefit analysis may include calculating an upcone benefit and a downcone benefit for groups of transistors coupled to one or more inputs and outputs, respectively.
摘要翻译：在一个实施例中，用于在集成电路上选择晶体管阈值电压的方法可以包括例如为选定的晶体管组（例如单元实例）分配第一阈值电压，以及确定选择的晶体管组中的哪一个以分配第二阈值电压，即低于第一阈值电压，通过迭代地执行成本/效益分析。该方法还可以包括通过迭代地执行成本/效益分析来确定具有第三阈值电压的所选择的晶体管组中的哪一个以分配第一阈值电压。成本/效益分析可以包括计算每组所选择的晶体管组的成本/效益比。此外，成本/效益分析可以包括分别计算耦合到一个或多个输入和输出的晶体管组的升序优点和降压益处。

10. 发明授权

US06487653B1 Method and apparatus for denormal load handling 有权
标题翻译：用于异常负载处理的方法和装置
公开(公告)号：US06487653B1
公开(公告)日：2002-11-26
申请号：US09383138
申请日：1999-08-25
申请人： Stuart F. Oberman , Stephan G. Meier , Jeffrey E. Trull
发明人： Stuart F. Oberman , Stephan G. Meier , Jeffrey E. Trull
IPC分类号： G06F738
CPC分类号： G06F9/3836 , G06F7/49905 , G06F9/30025 , G06F9/30043 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3873
摘要： A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform normal loads and detect denormal loads in a single clock cycle. The microprocessor temporarily stores each scheduled floating point instruction in a reissue buffer for at least one clock cycle. When a denormal load instruction is detected, the microprocessor is configured to add one or more stages to the floating point load pipeline to allow the denormal value to complete the conversion to an internal format. The longer pipeline is then used for all loads that follow the denormal load until there is an idle clock cycle or an abort occurs. At that point, the pipeline reverts back to its original shorter state. In addition, the microprocessor may be configured to cancel instructions scheduled assuming the denormal load would take only one clock cycle to complete. The canceled instruction is then “replayed” during a later clock cycle from the reissue buffer. A method for performing denormal loads and a computer system are also disclosed.
摘要翻译：公开了一种被配置为将其浮点负载流水线长度从一个阶段长度动态地切换到多于一个阶段的微处理器。微处理器可以在单个时钟周期内执行正常负载并检测异常负载。微处理器将至少一个时钟周期的每个调度的浮点指令临时存储在再发行缓冲器中。当检测到非正常加载指令时，微处理器被配置为向浮点加载流水线添加一个或多个级，以允许异常值完成到内部格式的转换。然后，较长的流水线将用于跟随异常负载的所有负载，直到发生空闲时钟周期或中止发生。在这一点上，管道恢复到原来的较短状态。此外，微处理器可以被配置为取消预定的指令，假设正常负载仅需要一个时钟周期来完成。然后在从重新发行缓冲区的较后时钟周期内“取消”取消的指令。还公开了一种用于执行异常负载的方法和计算机系统。

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