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1. 发明授权

US5668709A Switched capacitor current source 失效
标题翻译：开关电容电流源
公开(公告)号：US5668709A
公开(公告)日：1997-09-16
申请号：US398395
申请日：1995-03-02
申请人： John Edwin Gersbach , Masayuki Hayashi
发明人： John Edwin Gersbach , Masayuki Hayashi
IPC分类号： G05F3/24 , H02M3/07 , H02M3/18
CPC分类号： H02M3/07 , G05F3/242
摘要： A switched capacitor, integrated circuit employing at least one non-linear capacitor charged and discharged in response to a reference frequency includes a first conductive device for charging the non-linear capacitor to the supply voltage in response to one polarity of the reference frequency, and a second conductive device for discharging the non-linear capacitor in response to the opposite polarity of the reference frequency to a voltage level opposite that of the voltage source minus the threshold voltage of a third conductive device in the discharge path. Preferably, a pair of non-linear capacitors are employed, each being charged on alternate half cycles of the reference frequency, and the non-linear capacitors are accumulator capacitors. The circuit also include means for rapidly initiating the charging and discharging of said capacitors and for precluding changes in the state of charge or discharge thereof due to parasitic diodes in the circuit.
摘要翻译：开关电容器，采用响应于参考频率充电和放电的至少一个非线性电容器的集成电路包括用于响应于参考频率的一个极性而将非线性电容器充电到电源电压的第一导电装置，以及第二导电装置，用于响应于参考频率的相反极性而将非线性电容器放电到与电压源相反的电压电平减去放电路径中的第三导电装置的阈值电压。优选地，使用一对非线性电容器，每一个在基准频率的交替的半周期上被充电，并且非线性电容器是蓄电池电容器。电路还包括用于快速启动所述电容器的充电和放电的装置，并且用于阻止由于电路中的寄生二极管引起的充电或放电状态的改变。

2. 发明授权

US5668503A System and method for calibrating damping factor or analog PLL 失效
标题翻译：用于校准模拟PLL阻尼系数的系统和方法
公开(公告)号：US5668503A
公开(公告)日：1997-09-16
申请号：US645370
申请日：1996-05-13
申请人： John Edwin Gersbach , Masayuki Hayashi
发明人： John Edwin Gersbach , Masayuki Hayashi
IPC分类号： H03L7/089 , H03L7/095 , H03L7/10 , H03L7/183
CPC分类号： H03L7/095 , H03L7/0898 , H03L7/10 , H03L7/183 , H03L2207/04 , Y10S331/02
摘要： Calibration systems and techniques for analog phase-lock loops (PLLs) providing the capability to dynamically maintain a constant damping factor. Damping factor is calibrated by automatically setting a reference bias current I.sub.r to the PLL's charge pump such that the charge current I.sub.c output therefrom maintains the desired PLL damping characteristic. The technique presented involves selecting a known first frequency F.sub.1 and allowing the PLL circuit to reach steady state, after which a known second frequency F.sub.2 is applied and the PLL circuit is monitored to determine whether steady state at this second frequency F.sub.2 is accomplished within a predetermined target time T.sub.x, which corresponds to the desired damping factor. The determination of whether lock occurs within the target time T.sub.x is then employed to automatically setting the reference current I.sub.r.
摘要翻译：用于模拟锁相环（PLL）的校准系统和技术提供动态维持恒定阻尼因子的能力。通过将参考偏置电流Ir自动设置到PLL的电荷泵来校准阻尼因子，使得从其输出的充电电流Ic保持期望的PLL阻尼特性。所提出的技术涉及选择已知的第一频率F1并使PLL电路达到稳定状态，之后施加已知的第二频率F2，并且监视PLL电路以确定在该第二频率F2下的稳态是否在预定的目标时间Tx，其对应于期望的阻尼因子。然后采用在目标时间Tx内发生锁定的确定来自动设置参考电流Ir。

3. 发明授权

US5739725A Digitally controlled oscillator circuit 失效
标题翻译：数字振荡电路
公开(公告)号：US5739725A
公开(公告)日：1998-04-14
申请号：US593754
申请日：1996-01-29
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas, Jr.
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas, Jr.
IPC分类号： H03L7/089 , H03L7/093 , H03L7/099 , H03L7/183 , H03L7/06
CPC分类号： H03L7/0997 , H03L7/089 , H03L2207/06 , H03L2207/50 , H03L7/093 , H03L7/183
摘要： A variable frequency oscillator circuit includes a ring oscillator circuit, a plurality of adjustment means for adjusting an output frequency of the ring oscillator circuit, at least one of the adjustment means having monotonic behavior, adapted to switch between first adjustment levels at a first rate and at least one of the adjustment means having non-monotonic behavior, adapted to switch between second adjustment levels at a second rate which is less than the first rate, such that the means having monotonic behavior adjusts for monotonicity errors which occur during switching.
摘要翻译：可变频率振荡器电路包括环形振荡器电路，用于调节环形振荡器电路的输出频率的多个调整装置，具有单调性能的调节装置中的至少一个适于以第一速率在第一调整电平和调节装置中的至少一个具有非单调行为，适于以小于第一速率的第二速率在第二调整水平之间切换，使得具有单调行为的装置调整为在切换期间发生的单调性误差。

4. 发明授权

US5838205A Variable-speed phase-locked loop system with on-the-fly switching and method therefor 失效
标题翻译：具有动态切换的变速锁相环系统及其方法
公开(公告)号：US5838205A
公开(公告)日：1998-11-17
申请号：US801546
申请日：1997-02-18
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
IPC分类号： H03L7/22 , H03L7/07
CPC分类号： H03L7/07
摘要： According to the preferred embodiment, a phase-locked loop system is provided that overcomes the limitations of the prior art by providing the ability to switch output frequencies without a disruption in the phase lock of the output signal. The system uses a first phase-locked loop coupled with a second phase lock-loop such that their output signals are phase aligned and a switching mechanism for switching between the first phase lock output signal and the second phase lock loop output signal. The system is thus able to switch the frequency of its output without a disruption in the phase-lock of the signal.
摘要翻译：根据优选实施例，提供了一种锁相环系统，其通过提供切换输出频率而不会在输出信号的锁相中断的能力来克服现有技术的限制。该系统使用与第二锁相环耦合的第一锁相环，使得它们的输出信号是相位对准的，以及用于在第一锁相输出信号和第二锁相环输出信号之间切换的开关机构。因此，该系统能够切换其输出的频率而不会在信号的相位锁定中中断。

5. 发明授权

US5757238A Fast locking variable frequency phase-locked loop 失效
标题翻译：快速锁定可变频率锁相环
公开(公告)号：US5757238A
公开(公告)日：1998-05-26
申请号：US699296
申请日：1996-08-19
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
IPC分类号： H03L7/089 , H03L7/099 , H03L7/189 , H03L7/18
CPC分类号： H03L7/0995 , H03L7/089 , H03L7/189 , H03L2207/06
摘要： According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock. Thus, the phase-locked loop can quickly achieve phase lock at the different operating frequency.
摘要翻译：根据本发明的优选实施例，提供了一种锁相环，其克服了现有技术的限制，通过促进快速锁定转换到不同的输出频率。锁相环包括以各种选定频率提供锁相环输出信号的振荡器; 反馈分配器相位比较器用于存储对应于所选择的输出频率的锁相环控制信息的存储器存储机构; 以及数字电路机构，其在转换到不同的输出频率时从存储器存储机构接收控制信息。控制信息包括对应于不同输出频率处的输出信号的最后记录的相位差的数字计数器值。在转换时，该信息直接加载到数字电路机制，减少了相位比较器操作驱动PLL锁定所需的时间和时间。因此，锁相环可以在不同的工作频率下快速实现锁相。

6. 发明授权

US6031403A Pull-up and pull-down circuits 失效
标题翻译：上拉和下拉电路
公开(公告)号：US6031403A
公开(公告)日：2000-02-29
申请号：US748453
申请日：1996-11-13
申请人： John Edwin Gersbach
发明人： John Edwin Gersbach
IPC分类号： H03K3/356 , H03K17/22 , H03K19/0175 , H03K3/037
CPC分类号： H03K3/356008 , H03K17/223
摘要： According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC current. In one embodiment a pull-up/pull-down circuit is provided that powers up to a first state with the pull-up node high and the pull-down node low, and that can be toggled from one state to another. A second embodiment provides a pull-up or pull-down circuit that powers up to the desired state and can be disabled by pulling the pull-up node low or pulling the pull-down node high. The circuits remain disabled until the power to the circuit is cycled.
摘要翻译：根据本发明的优选实施例，提供使用具有不同阈值电压的晶体管的上拉/下拉电路，以确保上电到正确的预定状态。这些电路能够在绘制非常小的直流电流的同时上下保持节点。在一个实施例中，提供了上拉/下拉电路，其上拉节点为高并且下拉节点为低电平，并且可以从一个状态切换到另一状态。第二实施例提供上电或下拉电路，其上电至期望状态，并且可以通过将上拉节点拉低或拉低下拉节点而被禁用。电路保持禁用，直到电路的电源循环。

7. 发明授权

US5724008A Phase-locked loop with charge distribution 失效
标题翻译：带电荷分配的锁相环
公开(公告)号：US5724008A
公开(公告)日：1998-03-03
申请号：US641862
申请日：1996-05-02
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
IPC分类号： H03L7/089 , H03L7/093 , H03L7/183
CPC分类号： H03L7/093 , H03L7/0891 , H03L7/183
摘要： According to the preferred embodiment, an improved feedforward path is provided that improves the frequency response and reduces the output jitter of a phase-locked loop. Specifically, the frequency response is improved by providing a zero in the frequency response of the phase-locked loop by means of a feedforward path. The feedforward path delivers a feedforward charge to the oscillator of the phase-locked loop. According to the preferred embodiment, the feedforward path reorders the feedforward charge, such that the feedforward charge is stored and distributed equally across all the phase-locked loop output signal sub-cycles.
摘要翻译：根据优选实施例，提供改进的前馈路径，其改善了频率响应并且降低了锁相环的输出抖动。具体地，通过借助于前馈路径在锁相环的频率响应中提供零来提高频率响应。前馈路径为锁相环的振荡器提供前馈电荷。根据优选实施例，前馈路径重新排列前馈电荷，使得前馈电荷被存储并均匀分布在所有锁相环输出信号子周期上。

8. 发明授权

US5666118A Self calibration segmented digital-to-analog converter 失效
公开(公告)号：US5666118A
公开(公告)日：1997-09-09
申请号：US688452
申请日：1996-07-30
申请人： John Edwin Gersbach
发明人： John Edwin Gersbach
IPC分类号： H03M1/10 , H03M1/68 , H03M1/74
CPC分类号： H03M1/1052 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A method of self calibration for a segmented digital-to-analog converter is provided. The segmented digital-to-analog converter converts a digital input code to an analog output consisting of an analog output step and an analog calibration factor. The method comprises the step of determining a trim value for each segment of a segmented DAC. The method continues by storing the trim values in memory. Then, the trim values for a plurality of segments preselected to be enabled by a given digital input signal are summed, thereby producing a digital calibration factor associated with each given digital input signal. Last, storing each digital calibration factor in memory at an address corresponding to the associated digital input signal. Thereafter, when a particular digital input signal is received by the DAC, the preselected plurality of segmented current sources are switched to produce the analog output step, and the corresponding digital calibration factor is converted to the analog calibration factor and switched to the output of the segmented DAC.

9. 发明授权

US6118261A Slew rate control circuit 失效
标题翻译：压摆率控制电路
公开(公告)号：US6118261A
公开(公告)日：2000-09-12
申请号：US148452
申请日：1993-11-08
申请人： Charles Karoly Erdelyi , John Edwin Gersbach
发明人： Charles Karoly Erdelyi , John Edwin Gersbach
IPC分类号： H03K17/16 , H03K19/003 , G05F3/16 , H02M3/18
CPC分类号： H03K19/00361 , H03K17/163
摘要： A noise limited, video, digital to analog converter having an output transition time control with multiple discrete transition times. This is accomplished by a DAC control circuit in which the slew rate of the current is controlled by providing set current levels in the inverters that drive the DAC output current switches thus limiting the current available for charging and discharging the capacitance on the nodes which control the output signal. Additional control is provided by voltage clamping of these nodes which reduces the input voltage to the analog output and results in a cleaner output waveform.By so regulating and controlling the charging and discharging of these nodes, the variations in operation of the circuit due to the process used to produce the circuit in integrated form as well as temperature and supply voltage are further substantially reduced.
摘要翻译：具有具有多个离散转换时间的输出转换时间控制的噪声限制，视频，数模转换器。这是通过DAC控制电路实现的，其中通过在驱动DAC输出电流开关的逆变器中设置电流电平来控制电流的转换速率，从而限制可用于对控制输出信号。通过这些节点的钳位来提供额外的控制，从而将输入电压降低到模拟输出，并产生更清洁的输出波形。通过这样调节和控制这些节点的充电和放电，由于用于产生集成形式的电路的工艺以及温度和电源电压，电路的工作变化进一步显着降低。

10. 发明授权

US3982171A Gate current source 失效
标题翻译：门电流源
公开(公告)号：US3982171A
公开(公告)日：1976-09-21
申请号：US430276
申请日：1974-01-02
申请人： John Edwin Gersbach
发明人： John Edwin Gersbach
IPC分类号： G05F1/56 , G05F3/22 , G05F3/26 , H03K17/04 , G05F3/08
CPC分类号： G05F3/22
摘要： A gated current source providing a fast rise time, minimal delay and improved output current tolerance utilizes a non-linear feedback loop between first and second transistors and an appropriate proportioning of resistances coupled to a collector electrode of one of the transistors. The first transistor has its emitter electrode connected to the base electrode of the second transistor and the collector electrode of the second transistor is coupled to the base electrode of the first transistor through a diode. An input pulse is applied to the base electrode of the first transistor through a first resistor and a second resistor having an impedance value relatively low compared with that of the first resistor is connected to the collector electrode of the second transistor. A third transistor, acting as a current sink, has its base electrode connected to the base electrode of the second transistor at which a reference voltage used as a control voltage is produced. A conventional voltage source is suitably coupled to each of the transistors.
摘要翻译：提供快速上升时间，最小延迟和改善的输出电流容限的门控电流源利用第一和第二晶体管之间的非线性反馈环路以及耦合到晶体管之一的集电极的适当的电阻比例。第一晶体管的发射电极连接到第二晶体管的基极，第二晶体管的集电极通过二极管耦合到第一晶体管的基极。通过第一电阻将输入脉冲施加到第一晶体管的基极，并且与第一电阻相比阻抗值相对低的第二电阻器连接到第二晶体管的集电极。作为电流吸收器的第三晶体管的基极连接到第二晶体管的基极，在该基极处产生用作控制电压的基准电压。传统的电压源适当地耦合到每个晶体管。

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