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1. 发明授权

US06345356B1 Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs 失效
标题翻译：用于记分板的IOP的基于软件的调度失速机制的方法和装置
公开(公告)号：US06345356B1
公开(公告)日：2002-02-05
申请号：US09354498
申请日：1999-07-16
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Robert Greg McDonald
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Robert Greg McDonald
IPC分类号： G06F9312
CPC分类号： G06F9/3836 , G06F9/30018 , G06F9/30079 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No Operation—Internal Operations (NOP—IOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.
摘要翻译：发出虚拟指令，其次是几组无操作（NOP）。指令定序器单元（ISU）检测虚拟指令并停止流水线，直到记分板指示XER计数有效。从记分板专用寄存器（SPR）读取后，在写入和读取SPR IOP之间插入无操作内部操作（NOP-IOP），以允许在读取SPR IOP测试之前激活ISU记分板机制。使用读写读取序列：从记分板SPR中读取字符串计数字段，将该值写回相同的SPR，然后再次执行SPR的读取。预定数量的虚拟IOP跟随初始伪读取，以防止字串计数字段的值被读取太快。

2. 发明授权

US06442675B1 Compressed string and multiple generation engine 失效
标题翻译：压缩字符串和多代引擎
公开(公告)号：US06442675B1
公开(公告)日：2002-08-27
申请号：US09363464
申请日：1999-07-29
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le
IPC分类号： G06F938
CPC分类号： G06F9/30043 , G06F9/3017
摘要： A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the operations in the string instruction and whether or not the instructions need to be generated.
摘要翻译：提供通用的可编程数据流状态机以接收关于特定字符串指令的信息。字符串指令被解析为字符串指令中包含的所有操作。构成字符串指令的操作被路由到并行功能单元并执行。状态机在字符串指令中操作操作的大小以及是否需要生成指令。

3. 发明授权

US06430678B1 Scoreboard mechanism for serialized string operations utilizing the XER 失效
标题翻译：使用XER的串行字符串操作的记分板机制
公开(公告)号：US06430678B1
公开(公告)日：2002-08-06
申请号：US09363463
申请日：1999-07-29
申请人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
发明人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
IPC分类号： G06F930
CPC分类号： G06F9/30018 , G06F9/3017 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.
摘要翻译：通过使用指令排序器单元记分板提供XER记分板功能。如果XER由前一条指令使用，记分板位将被置位。如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。执行访问指令后，记分板位被清除。

4. 发明授权

US06286094B1 Method and system for optimizing the fetching of dispatch groups in a superscalar processor 有权
标题翻译：用于优化超标量处理器中调度组的获取的方法和系统
公开(公告)号：US06286094B1
公开(公告)日：2001-09-04
申请号：US09263663
申请日：1999-03-05
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.
摘要翻译：公开了一种用于确定处理系统中是否需要调度槽的方法和系统。所述方法和系统包括多个预解码比特，以提供路由信息并利用所述预解码比特来允许指令被引导到特定解码时隙，并且在不检查指令的情况下服从调度约束。该预编码系统方案的目的是为了提供关于指令分组的可能性最大的信息，而不增加使用该信息进行解码和组形成的逻辑的复杂性。在优选实施例中，分析可以并行发出的每个指令的预解码位，并且为指令流内的每个可能的起始位置保留多路复用器控制。

5. 发明授权

US06480931B1 Content addressable storage apparatus and register mapper architecture 有权
标题翻译：内容可寻址存储设备和寄存器映射器架构
公开(公告)号：US06480931B1
公开(公告)日：2002-11-12
申请号：US09434802
申请日：1999-11-05
申请人： Taqi Nasser Buti , Peter Juergen Klim , Hung Qui Le , Robert Greg McDonald
发明人： Taqi Nasser Buti , Peter Juergen Klim , Hung Qui Le , Robert Greg McDonald
IPC分类号： G06F1202
CPC分类号： G11C15/04 , G06F9/3836 , G06F9/3838 , G06F9/384 , G11C15/00
摘要： A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the actual comparisons occur. The CAM cell contains only latches to hold the CAM stored bit of data and a multi-port MUX to update the CAM content. The CAM bits are driven to the match arrays for match generation. The structure of the CAM and search engine facilitates implementation of the register mapper as a group of custom arrays. Each array is dedicated to execute a specific function. All of the arrays are aligned and each row of an array is devoted to one register to keep current state, shadow state and controls for that register. In an exemplary embodiment, eight custom arrays are used to execute various functions of the register mapper.
摘要翻译：提供非常规CAM（内容可寻址存储器）和寄存器映射器组织和电路实现，其允许同时执行大量CAM搜索。所有比较电路都放置在CAM外部，在实际比较发生的单独的匹配数组中。 CAM单元仅包含用于保存CAM存储的数据位的锁存器和用于更新CAM内容的多端口MUX。 CAM位被驱动到匹配数组以进行匹配生成。 CAM和搜索引擎的结构有助于将寄存器映射器实现为一组自定义阵列。每个阵列专用于执行特定功能。所有数组都对齐，数组的每一行都用于一个寄存器，以保持该寄存器的当前状态，阴影状态和控制。在示例性实施例中，八个定制阵列用于执行寄存器映射器的各种功能。

6. 发明授权

US06336183B1 System and method for executing store instructions 失效
标题翻译：执行存储指令的系统和方法
公开(公告)号：US06336183B1
公开(公告)日：2002-01-01
申请号：US09259140
申请日：1999-02-26
申请人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
发明人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F9312
CPC分类号： G06F9/3889 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.
摘要翻译：在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

7. 发明授权

US06289428B1 Superscaler processor and method for efficiently recovering from misaligned data addresses 失效
标题翻译：超标量处理器和方法可以有效地从不对齐的数据地址中恢复
公开(公告)号：US06289428B1
公开(公告)日：2001-09-11
申请号：US09366599
申请日：1999-08-03
申请人： John Edward Derrick , Hung Qui Le , David James Shippy , Larry Edward Thatcher
发明人： John Edward Derrick , Hung Qui Le , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1202
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/04
摘要： A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment. The first and second data segments are merged together. All of the instructions executed by the processor are constrained by the memory boundary and do not access memory across the memory boundary.
摘要翻译：公开了一种超标量处理器和方法，用于从未对准的数据地址有效地恢复。处理器包括划分成多个可寻址存储器单元的存储器件。多个可寻址存储器单元中的每一个具有第一多个字节的宽度。确定存储器访问指令中包括的数据地址是否不对齐。如果数据地址包括位于第一可寻址存储器单元中的第一数据段和位于第二可寻址存储器单元中的第二数据段，其中第一和第二数据段由可寻址存储器单元边界分隔，则该数据地址未对准。响应于确定数据地址未对准，执行访问第一存储器单元并获得第一数据段的第一内部指令。执行访问第二存储器单元并获得第二数据段的第二内部指令。第一和第二数据段合并在一起。由处理器执行的所有指令都受到存储器边界的约束，并且不会跨越存储器边界访问存储器。

8. 发明授权

US08347068B2 Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor 有权
标题翻译：多模式寄存器重命名机制，通过在同时多线程微处理器中的顺序和无序指令处理之间切换时，通过从寄存器重命名缓冲器切换物理寄存器来增加逻辑寄存器
公开(公告)号：US08347068B2
公开(公告)日：2013-01-01
申请号：US11696363
申请日：2007-04-04
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.
摘要翻译：多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

9. 发明授权

US07904661B2 Data stream prefetching in a microprocessor 失效
标题翻译：数据流在微处理器中预取
公开(公告)号：US07904661B2
公开(公告)日：2011-03-08
申请号：US11953637
申请日：2007-12-10
申请人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
发明人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.
摘要翻译：在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。数据预取请求被分配与数据流以反映确定的数据流的深度。分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。由处理器执行的指令中的预取控制位控制预取硬件配置。

10. 发明授权

US07827443B2 Processor instruction retry recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US07827443B2
公开(公告)日：2010-11-02
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

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