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1. 发明授权

US5602051A Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level 失效
标题翻译：在给定的堆叠级上制造具有电隔离和电连接区域的堆叠电气装置的方法
公开(公告)号：US5602051A
公开(公告)日：1997-02-11
申请号：US540387
申请日：1995-10-06
申请人： John E. Cronin , John K. DeBrosse , Hing Wong
发明人： John E. Cronin , John K. DeBrosse , Hing Wong
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L2924/0002
摘要： An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.
摘要翻译：公开了一种用于隔离彼此定位的电导体的改进方法。这些导体通常彼此接触，因为用于制造多个导电元件（例如非常致密的半导体结构）的图案化和蚀刻步骤有些不精确。该方法包括在下导体的上表面中形成凹部，然后用氧化物型材料至少部分地填充凹部。该方法在叠层电容器单元的构造中特别有价值。使用该技术制备的细胞也构成本发明的一部分。

2. 发明授权

US5610867A DRAM signal margin test method 失效
标题翻译： DRAM信号余量测试方法
公开(公告)号：US5610867A
公开(公告)日：1997-03-11
申请号：US535446
申请日：1995-09-28
申请人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4091 , G11C29/50 , G06F2201/81 , G11C11/401
摘要： In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.
摘要翻译：在本发明的优选实施例中，位线对通过一对高电阻通过门耦合到感测放大器。在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对之一。因此，数据从感测放大器传递到第二读出放大器和芯片外。数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。此外，由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。代替检测放大器参考电压，如现有技术的信号余量测试，通过改变单元信号来测试单元信号余量。可以选择VS来确定高和低信号余量。

3. 发明授权

US5963489A Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device 失效
标题翻译：用于可修复半导体存储器件中冗余字线替换的方法和装置
公开(公告)号：US5963489A
公开(公告)日：1999-10-05
申请号：US47086
申请日：1998-03-24
申请人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
发明人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/848
摘要： A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.
摘要翻译：一种用于修复半导体存储器件的方法和装置。提供行冗余替换布置以修复由第一多个冗余真字字线和第二多个冗余补码字线组成的存储器件，以同时替换相同的第一数量的第一正常字线和相同的第二数目的第正常补码字线。地址重排序方案优选地实现为字线选择器电路并由冗余控制逻辑和地址输入控制，允许冗余的真（补）字线在进行修复时替换正常的真（补）字线。冗余替换布置确保始终保持位图的一致性，而不管存储器件是以正常操作还是以冗余模式操作。这种方法引入了增加冗余替换的灵活性，而不影响列访问速度。

4. 发明授权

US5559739A Dynamic random access memory with a simple test arrangement 失效
标题翻译：动态随机存取存储器，具有简单的测试方案
公开(公告)号：US5559739A
公开(公告)日：1996-09-24
申请号：US535702
申请日：1995-09-28
申请人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G01R31/28 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4094 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4091 , G11C11/4094 , G11C29/50 , G11C11/401
摘要： A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux input. In this embodiment, the sense amp is connected between the mux's output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied. So, cell signal margin is tested by varying cell signal V.sub.S. V.sub.S may be selected to determine both a high and a low signal margin.
摘要翻译：一种动态随机存取存储器（DRAM），包括排列成行和列的存储器单元的阵列，每行中的字线响应于行地址，以及每列中的一对互补位线。 DRAM还包括连接在感测使能和该对互补位线之间的每列中的感测放大器。感测放大器是一对交叉耦合的NFET，其中NFET的源极连接到感测放大器使能。位线预充电连接到每对互补位线。位线预充电连接在互补位线对和参考电压之间。测试控制电路响应于测试控制信号选择性地将感测放大器禁用和位线对保持在预充电状态。连接在感测放大器和负载使能之间的主动感测放大器负载锁定读出放大器中的数据。主动感测放大器负载是连接到感测放大器的一对交叉耦合PFET，PFET的源极连接到负载使能。可选地，每列可以包括多个位线对，每对连接到多路复用器输入。在本实施例中，感测放大器连接在多路复用器的输出和读出放大器使能之间。由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。代替改变感测放大器参考电压，存储在单元中的电压是变化的。因此，通过改变单元信号VS来测试单元信号余量。可以选择VS来确定高和低信号余量。

5. 发明授权

US08456901B2 Spin-torque transfer magneto-resistive memory architecture 失效
标题翻译：自旋扭矩传递磁阻存储器架构
公开(公告)号：US08456901B2
公开(公告)日：2013-06-04
申请号：US13559672
申请日：2012-07-27
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种系统包括处理器和连接到处理器的存储器阵列，该存储器阵列包括第一存储器单元，该第一存储器单元包括具有连接到第一位线的第一端子和第二端子的第一磁性隧道结器件，以及具有源极端子的第一场效应晶体管连接到第二位线，连接到字线的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及包括第二磁性隧道结装置的第二存储单元，第二磁性隧道结装置具有第一端子连接至第三位线和第二端子，以及第二场效应晶体管，其源极端子连接到第二位线，连接到字线的栅极端子和连接到第二磁通道的第二端子的漏极端子连接装置。

6. 发明授权

US08023305B2 High density planar magnetic domain wall memory apparatus 有权
标题翻译：高密度平面磁畴壁存储装置
公开(公告)号：US08023305B2
公开(公告)日：2011-09-20
申请号：US12136091
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： G11C19/02 , G11C19/08
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

7. 发明申请

US20110173513A1 REFERENCE CELLS FOR SPIN TORQUE BASED MEMORY DEVICE 失效
标题翻译：基于旋转扭矩的记忆装置的参考电池
公开(公告)号：US20110173513A1
公开(公告)日：2011-07-14
申请号：US12684486
申请日：2010-01-08
申请人： John K. DeBrosse , Daniel C. Worledge
发明人： John K. DeBrosse , Daniel C. Worledge
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , H03M13/13
摘要： A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.
摘要翻译：一种读取和校正存储器件内的数据的方法，包括使用对应于每个数据位的多个参考单元读取数据字的每个数据位，对读取的数据位执行错误检测，以及当读取数据位时使用纠错码（ECC）检测错误，并将每个对应的参考单元写入其原始存储器状态。

8. 发明申请

US20080239784A1 HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS 有权
标题翻译：高密度平面磁畴壁记忆装置
公开(公告)号：US20080239784A1
公开(公告)日：2008-10-02
申请号：US12136091
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G11C19/00 , G11C11/00 , G11C7/00
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

9. 发明申请

US20080175043A1 METHOD AND APPARATUS FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE 失效
标题翻译：用于初始化切换MRAM器件的参考电池的方法和装置
公开(公告)号：US20080175043A1
公开(公告)日：2008-07-24
申请号：US11624707
申请日：2007-01-19
申请人： John K. DeBrosse , Mark C. H. Lamorey
发明人： John K. DeBrosse , Mark C. H. Lamorey
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/14 , G11C11/16 , G11C2207/2254
摘要： A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.
摘要翻译：确定制造的存储器阵列中的参考单元的初始状态的方法包括通过将通过参考单元的电流与通过一对数据单元的平均电流进行比较来执行参考单元的第一读取操作，并且存储第一次读取操作; 反转一对数据单元之一的值; 执行参考单元的第二读取操作，并存储第二读取操作的结果; 反转一对数据单元中的另一个的值; 执行参考单元的第三读取操作，并存储第三读取操作的结果。执行第一，第二和第三操作的结果的多数比较操作，其中多数比较操作的结果是参考单元的初始状态。

10. 发明授权

US07102916B2 Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption 失效
标题翻译：用于选择MRAM器件的各向异性轴角度以降低功耗的方法和结构
公开(公告)号：US07102916B2
公开(公告)日：2006-09-05
申请号：US10710281
申请日：2004-06-30
申请人： Philip L. Trouilloud , David W. Abraham , John K. DeBrosse , Daniel Worledge
发明人： Philip L. Trouilloud , David W. Abraham , John K. DeBrosse , Daniel Worledge
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A method for determining a desired anisotropy axis angle for a magnetic random access memory (MRAM) device includes selecting a plurality of initial values for the anisotropy axis angle and determining, for each selected initial value, a minimum thickness for at least one ferromagnetic layer of the MRAM device. The minimum thickness corresponds to a predefined activation energy of an individual cell within the MRAM device. For each selected value, a minimum applied magnetic field value in a wordline direction and a bitline direction of the MRAM device is also determined so as maintain the predefined activation energy. For each selected value, an applied power per bit value is calculated, wherein the desired anisotropy axis angle is the selected anisotropy axis angle corresponding to a minimum power per bit value.
摘要翻译：一种用于确定磁性随机存取存储器（MRAM）装置的期望的各向异性轴角的方法包括：为各向异性轴角选择多个初始值，并为每个所选择的初始值确定至少一个铁磁层的最小厚度 MRAM设备。最小厚度对应于MRAM设备内单个单元的预定激活能。对于每个选择的值，还确定MRAM装置的字线方向和位线方向上的最小施加磁场值，以便维持预定的激活能量。对于每个选择的值，计算每位值的施加功率，其中期望的各向异性轴角是对应于每位值的最小功率的所选各向异性轴角。

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