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1. 发明授权

US08133772B2 Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
标题翻译：用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
公开(公告)号：US08133772B2
公开(公告)日：2012-03-13
申请号：US13075271
申请日：2011-03-30
申请人： John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
发明人： John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

2. 发明授权

US07791123B2 Soft error protection structure employing a deep trench 失效
标题翻译：采用深沟槽的软错误保护结构
公开(公告)号：US07791123B2
公开(公告)日：2010-09-07
申请号：US12045190
申请日：2008-03-10
申请人： Ethan H. Cannon , John E. Barth, Jr. , Kerry Bernstein
发明人： Ethan H. Cannon , John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L27/108
CPC分类号： H01L29/66181 , G11C5/005 , H01L21/765 , H01L27/0629 , H01L27/11 , H01L29/945
摘要： A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.
摘要翻译：在具有第一导电类型的掺杂的半导体层中形成包含掺杂半导体填充部分的深沟槽，该掺杂半导体填充部分具有第一导电类型掺杂并被由下部具有第二导电类型掺杂的掩埋板包围。形成与掩埋板层相邻的第二导电类型的掺杂阱。掺杂半导体填充部分用作由辐射颗粒产生的第一导电类型的电荷的临时储存器，并且掩埋板层用作第二导电类型的电荷的临时储存器。掩埋板层和掺杂半导体填充部分形成电容器，并且提供对软错误的保护以防止在半导体层或掺杂阱中形成的器件。

3. 发明授权

US08053303B2 SOI body contact using E-DRAM technology 有权
标题翻译： SOI体接触采用E-DRAM技术
公开(公告)号：US08053303B2
公开(公告)日：2011-11-08
申请号：US13075552
申请日：2011-03-30
申请人： John E. Barth, Jr. , Kerry Bernstein , Francis R. White
发明人： John E. Barth, Jr. , Kerry Bernstein , Francis R. White
IPC分类号： H01L21/8238
CPC分类号： H01L29/78615
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。

4. 发明授权

US07989893B2 SOI body contact using E-DRAM technology 有权
公开(公告)号：US07989893B2
公开(公告)日：2011-08-02
申请号：US12200482
申请日：2008-08-28
申请人： John E. Barth, Jr. , Kerry Bernstein , Francis R. White
发明人： John E. Barth, Jr. , Kerry Bernstein , Francis R. White
IPC分类号： H01L27/01 , H01L29/786
CPC分类号： H01L29/78615
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.

5. 发明授权

US08263472B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08263472B2
公开(公告)日：2012-09-11
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/76
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

6. 发明授权

US08097525B2 Vertical through-silicon via for a semiconductor structure 有权
标题翻译：用于半导体结构的垂直通硅硅通孔
公开(公告)号：US08097525B2
公开(公告)日：2012-01-17
申请号：US12201580
申请日：2008-08-29
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
摘要翻译：半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

7. 发明授权

US08080851B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 有权
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08080851B2
公开(公告)日：2011-12-20
申请号：US12201462
申请日：2008-08-29
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L23/62
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：公开了半导体结构。半导体结构包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层设置在掩埋绝缘体层正下方并形成导电路径的第二极性类型的带区域，设置在本体衬底中并与带区接触的第二极性类型的阱区，填充有导电的深沟槽设置在阱区内的第一极性类型的材料以及由深沟槽的下部和阱区之间的接合部限定的静电放电（ESD）保护二极管。

8. 发明授权

US07898078B1 Power connector/decoupler integrated in a heat sink 有权
标题翻译：集成在散热器中的电源连接器/解耦器
公开(公告)号：US07898078B1
公开(公告)日：2011-03-01
申请号：US12568837
申请日：2009-09-29
申请人： Kerry Bernstein , John E. Barth, Jr.
发明人： Kerry Bernstein , John E. Barth, Jr.
IPC分类号： H01L23/36
CPC分类号： H01L23/5286 , H01L23/36 , H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06589 , H01L2924/1305 , H01L2924/00
摘要： Two sets of conductor fins are formed on a topmost surface of stacked semiconductor chips. The two sets of conductor fins are electrically isolated from each other, and function as radiators that dissipate heat from the stacked semiconductor chips. Conductive wiring structures are formed on each set of conductor fins to supply electrical power and electrical grounding to the stacked semiconductor chips. The bottommost surface of the stacked semiconductor chips may be bonded to a packaging substrate. Since the semiconductor fins above provide electrical power supply and electrical grounding, a higher fraction of electrical connections between the bottommost surface of the stacked semiconductor chips and the packaging substrate may be employed for input and output signal transmission without adverse impact on heat dissipation of the stacked semiconductor chips. The conductive fins function as power connectors. Decoupling capacitors including the conductive fins and dielectric portions therebetween may be formed.
摘要翻译：在堆叠的半导体芯片的最上表面上形成两组导体散热片。这两组导体翅片彼此电隔离，并且用作散发来自堆叠的半导体芯片的热量的散热器。在每组导体翅片上形成导电布线结构，以向堆叠的半导体芯片提供电力和电气接地。堆叠的半导体芯片的最底表面可以结合到封装衬底。由于上述半导体鳍片提供电力供应和电气接地，堆叠的半导体芯片的最底部表面和封装衬底之间的电连接的较高部分可用于输入和输出信号传输，而不会对堆叠的半导体芯片的散热产生不利影响半导体芯片。导电翅片用作电源连接器。可以形成包括其间的导电翅片和电介质部分的去耦电容器。

9. 发明授权

US08937345B2 Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact 有权
标题翻译：集成电路包括通过上覆触点与沟槽电容器电连接的有源晶体管
公开(公告)号：US08937345B2
公开(公告)日：2015-01-20
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108 , H01L21/768 , H01L23/485
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

10. 发明授权

US07668003B2 Dynamic random access memory circuit, design structure and method 有权
标题翻译：动态随机存取电路，设计结构与方法
公开(公告)号：US07668003B2
公开(公告)日：2010-02-23
申请号：US12108548
申请日：2008-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Hoki Kim , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Hoki Kim , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/10829 , G11C7/02 , G11C11/4099 , H01L27/10861 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
摘要翻译：公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

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