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1. 发明授权

US06493161B1 Pulse-mode writer 有权
标题翻译：脉冲模式写入
公开(公告)号：US06493161B1
公开(公告)日：2002-12-10
申请号：US09476016
申请日：1999-12-31
申请人： Carl F. Elliott , John D. Leighton , Sally A. Doherty
发明人： Carl F. Elliott , John D. Leighton , Sally A. Doherty
IPC分类号： G11B509
CPC分类号： G11B5/09
摘要： A pulse-mode data writing protocol is disclosed which reduces the time required to implement a transition in the direction of magnetization of a recording medium, and which reduces the total power required to encode a given data sequence. After a magnetic transition is encoded on the medium by generating a write current pulse through the write head, the write current through the recording head is reduced, thereby utilizing the spatial extent of the write bubble to encode the lack of a transition on the medium. Alternate configurations are disclosed for various scenarios of write bubble size versus maximum cell size, all utilizing the principle of the invention.
摘要翻译：公开了一种脉冲模式数据写入协议，其减少了在记录介质的磁化方向上实现转换所需的时间，并减少了编码给定数据序列所需的总功率。通过在写入头上产生写入电流脉冲对介质上的磁转换进行编码之后，通过记录头的写入电流减小，从而利用写入气泡的空间范围来对介质上的转换进行编码。公开了针对写入气泡尺寸与最大单元尺寸的各种情况的替代配置，所有这些都利用了本发明的原理。

2. 发明授权

US06256161B1 Echo cancellation for disk drive read circuit 有权
标题翻译：磁盘驱动器读取电路的回波消除
公开(公告)号：US06256161B1
公开(公告)日：2001-07-03
申请号：US09385788
申请日：1999-08-30
申请人： John D. Leighton , Sally A. Doherty
发明人： John D. Leighton , Sally A. Doherty
IPC分类号： G11B502
CPC分类号： G11B5/012 , G11B5/02 , G11B23/0007
摘要： Echo cancellation is provided in a disk drive circuit having a transducing head connected to a preamplifier circuit by an electrical interconnect with a first time delay, a first interface between the preamplifier and the electrical interconnect having a first reflection coefficient and a second interface between the transducing head and the electrical interconnect having a second reflection coefficient. The echo cancellation technique delays a preamplifier output signal with a second time delay, the second time delay being double the first time delay. The preamplifier output signal is also filtered so as to simulate the effects of the first and second reflection coefficients. The delayed and filtered signal is then subtracted from the preamplifier output signal, thereby removing echo content from the signal.
摘要翻译：在具有第一时间延迟的电互连连接到前置放大器电路的转换头的磁盘驱动电路中提供回波消除，前置放大器和电互连之间的第一接口具有第一反射系数和第二接口之间的转换头部和电互连具有第二反射系数。回波消除技术延迟具有第二时间延迟的前置放大器输出信号，第二时间延迟是第一时间延迟的两倍。前置放大器输出信号也被滤波，以模拟第一和第二反射系数的影响。然后从前置放大器输出信号中减去延迟和滤波的信号，从而消除信号中的回波内容。

3. 发明授权

US06707625B2 Dual-sense impedance-matched reader 有权
标题翻译：双重阻抗匹配读卡器
公开(公告)号：US06707625B2
公开(公告)日：2004-03-16
申请号：US09797399
申请日：2001-03-01
申请人： John D. Leighton , Carl Elliott , Jonathan P. Comeau
发明人： John D. Leighton , Carl Elliott , Jonathan P. Comeau
IPC分类号： G11B509
CPC分类号： H03F3/45089 , G11B5/012 , G11B5/02 , H03F2203/45318 , H03F2203/45548 , H03F2203/45574 , H03F2203/45722
摘要： A preamplifier system is connected through an interconnect to a read head. The preamplifier system includes a voltage-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output, and also includes a current-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output. A summing circuit is connected to combine the outputs of the voltage-sense preamplifier and the current-sense preamplifier. For optimal performance, the preamplifier system is impedance matched to the interconnect. The preamplifier system achieves excellent response due to impedance matching with acceptably low noise levels, since the correlated noise associated with the current-sense preamplifier is canceled at the summing circuit.
摘要翻译：前置放大器系统通过互连连接到读取头。前置放大器系统包括电压检测前置放大器，其具有通过互连连接到读取头并且具有至少一个输出的至少一个输入，并且还包括电流检测前置放大器，其具有通过互连连接到读取头的至少一个输入并具有至少一个输出。一个求和电路被连接起来来组合电压检测前置放大器和电流检测前置放大器的输出。为了获得最佳性能，前置放大器系统与互连阻抗匹配。由于与电流检测前置放大器相关联的相关噪声在求和电路处被消除，所以前置放大器系统由于具有可接受的低噪声电平的阻抗匹配而实现了出色的响应。

4. 发明授权

US6121800A Impedance matched, voltage-mode H-bridge write drivers 有权
标题翻译：阻抗匹配，电压模式H桥写入驱动器
公开(公告)号：US6121800A
公开(公告)日：2000-09-19
申请号：US152869
申请日：1998-09-14
申请人： John D. Leighton , Eric Groen
发明人： John D. Leighton , Eric Groen
IPC分类号： G11B5/00 , G11B5/02 , G11B5/09 , H03K17/66 , H03B1/00
CPC分类号： G11B5/022 , G11B5/02 , H03K17/663 , G11B2005/0013 , G11B5/09
摘要： A write driver for an inductive load includes load terminals for connection to an inductive load, and a driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. A voltage-mode H-bridge connected to the load terminals is operable to selectively supply a voltage across the load terminals and head. Program means operates the voltage-mode H-bridge for a predetermined time period following initiation of the respective first and second control signal to provide a voltage across the load terminals which quickly raises the write current to a steady state condition. Ringing is suppressed by employing an impedance-matched H-bridge for the driver circuit, the impedance-matched H-bridge having an impedance matched to the impedance of a transmission line connecting the load to the terminals.
摘要翻译：用于感性负载的写驱动器包括用于连接到感性负载的负载端子，以及响应于第一和第二控制信号的驱动电路，以在相应的第一和第二方向上提供驱动电流通过负载。连接到负载端子的电压模式H桥可操作以选择性地在负载端子和头部之间提供电压。编程装置在开始相应的第一和第二控制信号之后的预定时间段内操作电压模式H桥，以在负载端子两端提供电压，从而将写入电流快速地提升到稳定状态。通过对驱动电路采用阻抗匹配H桥来抑制振铃，阻抗匹配H桥具有与将负载连接到端子的传输线的阻抗匹配的阻抗。

5. 发明授权

US06785071B2 Disk drive writer waveform induced precompensation 有权
标题翻译：磁盘驱动器写入器波形引起预补偿
公开(公告)号：US06785071B2
公开(公告)日：2004-08-31
申请号：US10115303
申请日：2002-04-03
申请人： Carl F. Elliott , John D. Leighton
发明人： Carl F. Elliott , John D. Leighton
IPC分类号： G11B502
CPC分类号： G11B20/10194 , G11B5/012 , G11B5/035 , G11B5/09 , G11B20/10009 , G11B2005/001
摘要： A disk driver writer precompensation system modulates the write current waveform based on a pattern of data bits magnetically recorded on a medium in order to adjust the timing of magnetic transitions recorded on the medium.
摘要翻译：磁盘驱动器写入器预补偿系统基于磁记录在介质上的数据位的模式来调制写入电流波形，以便调节记录在介质上的磁转变的定时。

6. 发明授权

US5942934A On-chip regulator providing good high frequency rejection and noise filtering from the supply 失效
标题翻译：片上稳压器从电源提供良好的高频抑制和噪声滤波
公开(公告)号：US5942934A
公开(公告)日：1999-08-24
申请号：US890417
申请日：1997-07-09
申请人： Tuan V. Ngo , John D. Leighton
发明人： Tuan V. Ngo , John D. Leighton
IPC分类号： G05F3/22 , G05F3/26 , G05F1/10
CPC分类号： G05F3/265 , G05F3/222
摘要： A power supply filter has a primary current source coupled to a node carrying a power supply signal. The second end of the primary current source is coupled to an impedance that is further coupled to a low voltage node. A differential amplifier having an inverting input, a non-inverting input, and an output, has its non-inverting input coupled to the junction between the impedance and the primary current source. The output of the differential amplifier carries the filtered power supply signal and is coupled to a capacitance. The capacitance is coupled between the output and a lower voltage. A feedback path is coupled between the output and the inverting input.
摘要翻译：电源滤波器具有耦合到承载电源信号的节点的初级电流源。初级电流源的第二端耦合到进一步耦合到低电压节点的阻抗。具有反相输入，非反相输入和输出的差分放大器具有耦合到阻抗和主电流源之间的结的非反相输入。差分放大器的输出携带滤波后的电源信号并耦合到电容。电容耦合在输出和较低的电压之间。反馈路径耦合在输出和反相输入端之间。

7. 发明授权

US5721484A Power supply filter with active element assist 失效
标题翻译：具有有源元件辅助功能的电源滤波器
公开(公告)号：US5721484A
公开(公告)日：1998-02-24
申请号：US769125
申请日：1996-12-19
申请人： Tuan V. Ngo , John D. Leighton
发明人： Tuan V. Ngo , John D. Leighton
IPC分类号： G05F3/26 , G05F3/16
CPC分类号： G05F3/265
摘要： A power supply filter is constructed with a capacitive element and an active element coupled to a filtered node and an impedance coupled between the filtered node and a power supply node. The filtered node for carrying a filtered version of a power supply signal on the power supply node. The active element having electrical characteristics such that the addition of the active element to the power supply filter reduces the amount of capacitance needed from the capacitive element to achieve a desired pole frequency for a given voltage drop across the impedance element.
摘要翻译：电源滤波器由电容元件和耦合到滤波节点的有源元件和耦合在滤波后的节点与电源节点之间的阻抗构成。用于在电源节点上携带电源信号的滤波版本的滤波节点。具有电特性的有源元件使得将有源元件添加到电源滤波器减少了从电容元件所需的电容量，以达到阻抗元件上的给定电压降达到期望的极点频率。

8. 发明授权

US07339760B2 Integrated bias and offset recovery amplifier 有权
标题翻译：集成偏置和偏移恢复放大器
公开(公告)号：US07339760B2
公开(公告)日：2008-03-04
申请号：US10955775
申请日：2004-09-30
申请人： Jeffrey A. Gleason , John D. Leighton , Scott M. O'Brien
发明人： Jeffrey A. Gleason , John D. Leighton , Scott M. O'Brien
IPC分类号： G11B5/02
CPC分类号： G11B5/02 , G11B2005/0016 , G11B2005/0018 , H03F3/456 , H03F3/45748
摘要： A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.
摘要翻译：前置放大器电路连接到转换头，并具有集成偏置电路和偏移恢复电路。偏移恢复电路响应于从写入模式的转变而被读取更多，以提供表示跨导头的信号的输出信号。偏置电路由偏移恢复电路的输出信号驱动以偏置换能头。

9. 发明授权

US06512646B1 Impedance-matched write circuit 有权
标题翻译：阻抗匹配写电路
公开(公告)号：US06512646B1
公开(公告)日：2003-01-28
申请号：US09475909
申请日：1999-12-30
申请人： John D. Leighton , Raymond E. Barnett , Tuan V. Ngo
发明人： John D. Leighton , Raymond E. Barnett , Tuan V. Ngo
IPC分类号： H03B100
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B2005/0013
摘要： A write circuit selectively provides a write current through a write head in first and second opposite directions. The write circuit is connected to the write head by an interconnect, and has a positive supply level and a negative supply level. A first voltage source provides a first control voltage, and a second voltage source provides a second control voltage. A first resistor is provided between the first voltage source and the interconnect for impedance matching to the interconnect, and a second resistor is provided between the second voltage source and the interconnect for impedance matching to the interconnect. The first and second control voltages provide a transient voltage to the interconnect and provide a subsequent steady-state voltage to the interconnect.
摘要翻译：写入电路在第一和第二相反方向上选择性地提供写入电流通过写入头。写入电路通过互连连接到写入头，并且具有正的电源电平和负的电源电平。第一电压源提供第一控制电压，第二电压源提供第二控制电压。第一电阻器设置在第一电压源和互连件之间用于与互连件的阻抗匹配，并且第二电阻器设置在第二电压源和互连件之间用于与互连件的阻抗匹配。第一和第二控制电压为互连提供瞬态电压并向互连提供随后的稳态电压。

10. 发明授权

US4404439A Method and construction for vehicle brake pedal and switch assembly 失效
标题翻译：车辆制动踏板和开关组件的方法和结构
公开(公告)号：US4404439A
公开(公告)日：1983-09-13
申请号：US287882
申请日：1981-07-29
申请人： John D. Leighton
发明人： John D. Leighton
IPC分类号： B60T7/02 , B60Q1/44 , B60T7/04 , B60T7/06 , G05G1/38 , G05G1/487 , G05G9/00 , H01H3/14 , H01H13/16
CPC分类号： H01H13/16 , B60Q1/441 , B60T7/042 , B60T7/06 , B60W10/04 , B60W10/184 , B60W30/18109 , G05G1/30 , G05G1/487 , H01H3/14 , B60W2540/12 , B60W2710/06 , B60W2710/18 , B60W30/143 , Y10T74/20888
摘要： Two embodiments of improved brake light switches that are integrated into the brake pedal and are actuated by the application of pressure to the pedal. In one embodiment, the pedal pad is movable relative to the pedal and this relative movement effects closure of the switch.
摘要翻译：改进的制动灯开关的两个实施例被集成到制动踏板中并且通过向踏板施加压力来致动。在一个实施例中，踏板垫可相对于踏板移动，并且该相对移动会影响开关的闭合。

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