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1. 发明申请

US20150021999A1 GRID APPORTIONING BIMODAL POWER MODULE AND METHOD 审中-公开
标题翻译：网格分配双模功率模块和方法
公开(公告)号：US20150021999A1
公开(公告)日：2015-01-22
申请号：US13946858
申请日：2013-07-19
申请人： John A. Rodriguez
发明人： John A. Rodriguez
IPC分类号： H02J3/00
CPC分类号： H02J3/008 , H02J7/35 , Y04S50/10 , Y10T307/549
摘要： A system for storage and communication of electrical power generated at local renewable energy generations sites, for subsequent communication to the local power grid is disclosed. Employing electrical energy monitors and storage, locally generated electrical power is always communicated to the local grid within threshold parameters for sale and payment. Using timing components and software, the local generated energy can also be stored and communicated to the grid during determined times of day to yield the highest payment price.
摘要翻译：公开了一种用于存储和通信在当地可再生能源发电站产生的电力的系统，用于随后与当地电网的通信。采用电能监控和存储，本地生成的电力总是在门槛参数内传送到本地电网进行销售和支付。使用定时组件和软件，本地生成的能量也可以在一天的确定时间内存储并传送到电网，以获得最高的支付价格。

2. 发明授权

US07894234B2 F-SRAM before package solid data write 有权
标题翻译： F-SRAM前封装固体数据写入
公开(公告)号：US07894234B2
公开(公告)日：2011-02-22
申请号：US12502860
申请日：2009-07-14
申请人： John A. Rodriguez , Scott R. Summerfelt
发明人： John A. Rodriguez , Scott R. Summerfelt
IPC分类号： G11C11/22
CPC分类号： G11C14/00 , G11C8/10 , G11C11/412 , G11C14/0072
摘要： A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and then removing power from the integrated circuit. A process polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation, then removing power from the integrated circuit. A process of polarizing a programmable data storage component of an integrated circuit by polarizing corresponding ferroelectric capacitors in same orientations, then removing power from the integrated circuit. An integrated circuit containing a programmable data storage component and a ferroelectric capacitor polarization circuit that is configured to polarize a first data ferroelectric capacitor and a second data ferroelectric capacitor in desired polarization configurations by applying biases to a first state node, a second state node, a first plate node, and a second plate node.
摘要翻译：通过以相同的方向对强电介质电容器进行极化，然后从集成电路去除功率，来极化集成电路的可编程数据存储部件的过程。一种通过以相同的方向极化铁电电容器来对集成电路的可编程数据存储部件进行偏振的方法，然后从集成电路去除功率。通过以相同方向对相应的铁电电容器进行极化，然后从集成电路去除功率来偏振集成电路的可编程数据存储部件的过程。一种包含可编程数据存储部件和铁电电容器极化电路的集成电路，其被配置为通过将偏置应用于第一状态节点，第二状态节点，第二状态节点，第二状态节点，第一板节点和第二板节点。

3. 发明授权

US08753952B2 Integrated circuit with integrated decoupling capacitors 有权
标题翻译：具集成去耦电容的集成电路
公开(公告)号：US08753952B2
公开(公告)日：2014-06-17
申请号：US13330833
申请日：2011-12-20
申请人： Scott Robert Summerfelt , John A. Rodriguez , Huang-Chun Wen , Steven Craig Bartling
发明人： Scott Robert Summerfelt , John A. Rodriguez , Huang-Chun Wen , Steven Craig Bartling
IPC分类号： H01L21/20
CPC分类号： H01L27/0805 , H01L27/0207 , H01L27/06 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L29/92
摘要： Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
摘要翻译：用于集成去耦电容器的铁电电容器结构等。铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

4. 发明申请

US20130062733A1 Integrated Circuit with Integrated Decoupling Capacitors 有权
标题翻译：集成电路与集成去耦电容
公开(公告)号：US20130062733A1
公开(公告)日：2013-03-14
申请号：US13330833
申请日：2011-12-20
申请人： Scott Robert Summerfelt , John A. Rodriguez , Huang-Chun Wen , Steven Craig Bartling
发明人： Scott Robert Summerfelt , John A. Rodriguez , Huang-Chun Wen , Steven Craig Bartling
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L27/0207 , H01L27/06 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L29/92
摘要： Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
摘要翻译：用于集成去耦电容器的铁电电容器结构等。铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

5. 发明授权

US07085150B2 Methods for enhancing performance of ferroelectic memory with polarization treatment 有权
标题翻译：用极化处理提高铁电记忆性能的方法
公开(公告)号：US07085150B2
公开(公告)日：2006-08-01
申请号：US11017572
申请日：2004-12-20
申请人： John A. Rodriguez , Kezhakkedath R. Udayakumar
发明人： John A. Rodriguez , Kezhakkedath R. Udayakumar
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention facilitates data retention lifetimes for ferroelectric devices by improving switched polarization of ferroelectric memory cells. A ferroelectric memory device comprising ferroelectric memory cells is provided (702). A duration for applying a DC bias to the ferroelectric memory cells is selected (704) according to at least a desired switched polarization improvement. A magnitude for applying the DC bias to the ferroelectric memory cells is also selected (706) according to at least the desired switched polarization improvement. Further, an elevated temperature is selected for applying the DC bias to the ferroelectric memory cells is also selected (708) according to at least the desired switched polarization improvement. Subsequently, the DC bias is applied to the ferroelectric memory cells (710), which activates one or more inactive domains within the ferroelectric memory cells and increases initial polarization values.
摘要翻译：本发明通过改善铁电存储器单元的开关极化来促进强电介质器件的数据保留寿命。提供了包括铁电存储单元的铁电存储器件（702）。根据至少所需的开关极化改善来选择向铁电存储器单元施加DC偏压的持续时间（704）。根据至少所需的开关极化改善，也选择用于将DC偏压施加到铁电存储单元的幅度（706）。此外，根据至少所需的开关极化改善，还选择（708）将用于将DC偏压施加到铁电存储器单元的升高的温度。随后，将DC偏压施加到铁电存储单元（710），其激活铁电存储单元内的一个或多个非活性区域并增加初始极化值。

6. 发明授权

US06465307B1 Method for manufacturing an asymmetric I/O transistor 有权
标题翻译：制造不对称I / O晶体管的方法
公开(公告)号：US06465307B1
公开(公告)日：2002-10-15
申请号：US09997951
申请日：2001-11-30
申请人： P R Chidambaram , John A. Rodriguez
发明人： P R Chidambaram , John A. Rodriguez
IPC分类号： H01L21336
CPC分类号： H01L29/66659 , H01L21/28167 , H01L21/28194 , H01L21/823462 , H01L29/42368 , H01L29/7835 , Y10S438/981
摘要： According to one embodiment of the invention, a method of forming an asymmetric I/O transistor includes forming a first oxide layer outwardly from a semiconductor substrate, masking a first portion, less than a whole portion, of an I/O transistor region with a first photoresist layer, removing the first oxide layer from a core transistor region and a second portion of the I/O transistor region, removing the first photoresist layer, forming a second oxide layer outwardly from the substrate, forming gates for the core transistor region and the I/O transistor region, masking the first portion of the I/O transistor region with a second photoresist layer, doping a source region and a drain region of the core transistor region and a source region of the I/O transistor region with a first dopant, doping the source region and the drain region of the core transistor region and the source region of the I/O transistor region with a second dopant, removing the second photoresist layer, masking the core transistor region and the second portion of the I/O transistor region with a third photoresist layer, and doping a drain region of the I/O transistor region with a third dopant.
摘要翻译：根据本发明的一个实施例，形成非对称I / O晶体管的方法包括：从半导体衬底向外形成第一氧化物层，用I / O晶体管区域遮蔽I / O晶体管区域的小于整个部分的第一部分第一光致抗蚀剂层，从核心晶体管区域和I / O晶体管区域的第二部分去除第一氧化物层，去除第一光致抗蚀剂层，从衬底向外形成第二氧化物层，形成芯晶体管区域的栅极，以及 I / O晶体管区域，用第二光致抗蚀剂层掩蔽I / O晶体管区域的第一部分，将核心晶体管区域的源极区域和漏极区域以及I / O晶体管区域的源极区域用第一掺杂剂，用第二掺杂剂掺杂核心晶体管区域的源极区域和漏极区域和I / O晶体管区域的源极区域，去除第二光致抗蚀剂层，掩蔽并且具有第三光致抗蚀剂层的I / O晶体管区域的第二部分，并且用第三掺杂剂掺杂I / O晶体管区域的漏极区域。

7. 发明授权

US07889535B2 F-SRAM margin screen 有权
标题翻译： F-SRAM边界屏幕
公开(公告)号：US07889535B2
公开(公告)日：2011-02-15
申请号：US12491817
申请日：2009-06-25
申请人： John A. Rodriguez , Hugh P. McAdams , Scott R. Summerfelt , Steven Bartling
发明人： John A. Rodriguez , Hugh P. McAdams , Scott R. Summerfelt , Steven Bartling
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C14/00
摘要： A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.
摘要翻译：一种测试包含可编程数据存储部件的集成电路的过程，所述可编程数据存储部件包含耦合到互补状态节点的至少两个铁电电容器，其包括在召回操作之前施加干扰电压。此外，测试包含耦合到互补状态节点的至少两个铁电电容器的可编程数据存储部件的集成电路的处理，其包括调整干扰电压并确定屏蔽数据值和读取数据值是否符合用于确定限制干扰电压。

8. 发明申请

US20100027313A1 F-SRAM Before Package Solid Data Write 有权
标题翻译：封装前的F-SRAM数据写入数据
公开(公告)号：US20100027313A1
公开(公告)日：2010-02-04
申请号：US12502860
申请日：2009-07-14
申请人： John A. Rodriguez , Scott R. Summerfelt
发明人： John A. Rodriguez , Scott R. Summerfelt
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C14/00 , G11C8/10 , G11C11/412 , G11C14/0072
摘要： A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and then removing power from the integrated circuit. A process polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation, then removing power from the integrated circuit. A process of polarizing a programmable data storage component of an integrated circuit by polarizing corresponding ferroelectric capacitors in same orientations, then removing power from the integrated circuit. An integrated circuit containing a programmable data storage component and a ferroelectric capacitor polarization circuit that is configured to polarize a first data ferroelectric capacitor and a second data ferroelectric capacitor in desired polarization configurations by applying biases to a first state node, a second state node, a first plate node, and a second plate node.
摘要翻译：通过以相同的方向对强电介质电容器进行极化，然后从集成电路去除功率，来极化集成电路的可编程数据存储部件的过程。一种通过以相同的方向极化铁电电容器来对集成电路的可编程数据存储部件进行偏振的方法，然后从集成电路去除功率。通过以相同方向对相应的铁电电容器进行极化，然后从集成电路去除功率来偏振集成电路的可编程数据存储部件的过程。一种包含可编程数据存储部件和铁电电容器极化电路的集成电路，其被配置为通过将偏置应用于第一状态节点，第二状态节点，第二状态节点，第二状态节点，第一板节点和第二板节点。

9. 发明申请

US20100002488A1 F-SRAM Margin Screen 有权
标题翻译： F-SRAM边距屏幕
公开(公告)号：US20100002488A1
公开(公告)日：2010-01-07
申请号：US12491817
申请日：2009-06-25
申请人： John A. Rodriguez , Hugh P. McAdams , Scott R. Summerfelt , Steven Bartling
发明人： John A. Rodriguez , Hugh P. McAdams , Scott R. Summerfelt , Steven Bartling
IPC分类号： G11C11/22 , G11C5/14 , G11C11/24 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C14/00
摘要： A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.
摘要翻译：一种测试包含可编程数据存储部件的集成电路的过程，所述可编程数据存储部件包含耦合到互补状态节点的至少两个铁电电容器，其包括在召回操作之前施加干扰电压。此外，测试包含耦合到互补状态节点的至少两个铁电电容器的可编程数据存储部件的集成电路的处理，其包括调整干扰电压并确定屏蔽数据值和读取数据值是否符合用于确定限制干扰电压。

10. 发明授权

US6060372A Method for making a semiconductor device with improved sidewall junction capacitance 失效
标题翻译：制造具有改善的侧壁结电容的半导体器件的方法
公开(公告)号：US6060372A
公开(公告)日：2000-05-09
申请号：US823286
申请日：1997-03-21
申请人： Michael C. Smayling , Alister C. Young , John A. Rodriguez , Jihong Chen
发明人： Michael C. Smayling , Alister C. Young , John A. Rodriguez , Jihong Chen
IPC分类号： H01L21/28 , H01L21/762 , H01L21/8234 , H01L21/822 , H01L21/265
CPC分类号： H01L21/28123 , H01L21/76216 , H01L21/823481
摘要： A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.
摘要翻译：本发明的半导体器件（10）具有绝缘地设置在衬底之上的栅极（32），源极和漏极区域（36,38）设置在邻近栅极（32）的相对侧的衬底中的表面附近，以及设置在围绕源极和漏极区域（36,38）的基板的表面中并且限定活动的护城河区域（20）的场氧化物区域（26）。通道停止区域（24）设置在场氧化物区域（26）的下方，并且以预定的间隔与活动的护壕区域（20）间隔开。

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