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1. 发明授权

US08373441B1 Orienting voltage translators in input/output buffers 有权
标题翻译：定向输入/输出缓冲器中的电压转换器
公开(公告)号：US08373441B1
公开(公告)日：2013-02-12
申请号：US13236914
申请日：2011-09-20
申请人： John A. Milinichik , Peter J. Nicholas , Carol A. Huber , Antonio M. Marques , Daniel J. Delpero
发明人： John A. Milinichik , Peter J. Nicholas , Carol A. Huber , Antonio M. Marques , Daniel J. Delpero
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： G06F17/5068
摘要： Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.
摘要翻译：所描述的实施例提供了一种半导体器件，其包括芯和围绕芯的一个或多个输入/输出（I / O）缓冲器。 I / O缓冲器适于传输与核心的核心电路相关联的信号。 I / O缓冲器包括具有第一取向的I / O单元和具有第二取向的I / O单元。每个I / O单元具有相应的占空比中具有低电压晶体管的对应的转换器。第一定向I / O单元中的低电压晶体管具有第一取向，并且第二取向I / O单元中的低电压晶体管具有第一取向。第一定向I / O单元和第二定向I / O单元的脚印彼此兼容。

2. 发明授权

US07551020B2 Enhanced output impedance compensation 有权
标题翻译：增强的输出阻抗补偿
公开(公告)号：US07551020B2
公开(公告)日：2009-06-23
申请号：US11755955
申请日：2007-05-31
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/00384 , H04L5/16 , H04L25/0264
摘要： A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.
摘要翻译：用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

3. 发明授权

US07068074B2 Voltage level translator circuit 有权
标题翻译：电压电平转换电路
公开(公告)号：US07068074B2
公开(公告)日：2006-06-27
申请号：US10881192
申请日：2004-06-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.
摘要翻译：用于将参考第一电压电平的输入信号转换为参考第二电压电平的输出信号的电压电平转换器电路包括用于接收输入信号的输入级。输入级包括具有与其相关联的第一阈值电压的至少一个晶体管器件。电压电平转换器电路还包括可操作地存储表示输入信号的逻辑状态的信号的锁存电路。锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，第二阈值电压大于第一阈值电压。电压钳被可操作地连接在输入级和锁存电路之间，电压钳被配置成至少部分地基于呈现给输入级的控制信号来限制跨输入级的电压。电压电平转换器电路包括用于产生控制信号的参考发生器电路，控制信号的稳态值基本上等于第一电压电平。参考发生器电路被配置为响应于输入信号调整控制信号的电压电平。

4. 发明申请

US20080297226A1 Enhanced Output Impedance Compensation 有权
标题翻译：增强输出阻抗补偿
公开(公告)号：US20080297226A1
公开(公告)日：2008-12-04
申请号：US11755955
申请日：2007-05-31
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Antonio M. Marques , Bernard L. Morris
IPC分类号： G06G7/12
CPC分类号： H03K19/00384 , H04L5/16 , H04L25/0264
摘要： A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.
摘要翻译：用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

5. 发明授权

US07196561B2 Programmable reset signal that is independent of supply voltage ramp rate 有权
标题翻译：独立于电源电压斜坡率的可编程复位信号
公开(公告)号：US07196561B2
公开(公告)日：2007-03-27
申请号：US10925613
申请日：2004-08-25
申请人： Dipankar Bhattacharya , John C. Kriz , Duane J. Loeper , Antonio M. Marques
发明人： Dipankar Bhattacharya , John C. Kriz , Duane J. Loeper , Antonio M. Marques
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.
摘要翻译：用于产生复位信号的PUR电路包括用于接收参考电压的第一节点和用于接收相对于参考电压参考的电源电压的第二节点。电路还包括耦合在第一节点和第三节点之间的电压电平检测器，电压电平检测器被配置为在第三节点处产生第一控制信号。电压电平检测器包括具有与其相关联的第一阈值电压的第一晶体管。电阻元件耦合在第二节点和第三节点之间，电阻元件具有与之相关联的第一电阻值。该电路还包括具有耦合到第三节点并具有响应于第一控制信号产生第二控制信号的输出的反相器。逆变器包括具有与其相关联的第二阈值电压的第二晶体管，其低于第一阈值电压。电压电平检测器被配置为使得当电源电压小于第一电压时，第一控制信号基本上等于电源电压，并且当电源电压基本上等于或等于第一控制信号时，第一控制信号等于第二电压大于第一电压。第二电压小于逆变器的较低开关点，第一电压至少部分地基于第一阈值电压，复位信号是第二控制信号的函数。

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