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1. 发明授权

US07932156B2 Bipolar transistor having a second, base-comprising region consisting of a first layer, a second, constrictive, layer, and a third layer 有权
标题翻译：具有由第一层，第二层，缩缩层和第三层组成的第二基底包含区域的双极晶体管
公开(公告)号：US07932156B2
公开(公告)日：2011-04-26
申请号：US11997231
申请日：2006-07-26
申请人： Johannes J. T. M. Donkers , Wibo D. Van Noort , Francois Neuilly
发明人： Johannes J. T. M. Donkers , Wibo D. Van Noort , Francois Neuilly
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/26506 , H01L21/26513 , H01L29/0649 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/732
摘要： The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region (26,27) is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device (10) is possible thanks to its manufacture with a method of manufacturing according to the invention.
摘要翻译：本发明涉及具有衬底（12）和硅的半导体本体（11）的半导体器件（10），其包括具有发射极区域，基极区域和集电极区域（1,2,3）的双极晶体管的第一导电性类型，分别与所述第一导电类型和第一导电类型相反的第二导电类型，其中第一半导体区域（3）包括形成在半导体本体（11）中的集电极区域或发射极区域，其顶部存在包括基极区域的第二半导体区域（2），其上存在包括所述集电极区域和所述发射极区域中的另一个的第三半导体区域（1），所述半导体本体（11）设置有收缩部在第一和第二半导体区域（3,2）之间的过渡位置处，通过埋在半导体本体（11）中的电绝缘区域（26,27）形成该收缩）。根据本发明，形成在掩埋电绝缘区域（26,27）上方的半导体本体的一部分是单晶的。这使得器件的强大的侧向小型化并且导致晶体管的优异的高频特性。由于通过根据本发明的制造方法的制造，这种装置（10）是可能的。

2. 发明申请

US20090174034A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090174034A1
公开(公告)日：2009-07-09
申请号：US11997231
申请日：2006-07-26
申请人： Johannes J., T., M. Donkers , Wibo D. Van Noort , Francois Neuilly
发明人： Johannes J., T., M. Donkers , Wibo D. Van Noort , Francois Neuilly
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/7378 , H01L21/26506 , H01L21/26513 , H01L29/0649 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/732
摘要： The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region (26,27) is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device (10) is possible thanks to its manufacture with a method of manufacturing according to the invention.
摘要翻译：本发明涉及具有衬底（12）和硅的半导体本体（11）的半导体器件（10），其包括具有发射极区域，基极区域和集电极区域（1,2,3）的双极晶体管的第一导电性类型，分别与所述第一导电类型和第一导电类型相反的第二导电类型，其中第一半导体区域（3）包括形成在半导体本体（11）中的集电极区域或发射极区域，其顶部存在包括基极区域的第二半导体区域（2），其上存在包括所述集电极区域和所述发射极区域中的另一个的第三半导体区域（1），所述半导体本体（11）设置有收缩部在第一和第二半导体区域（3,2）之间的过渡位置处，通过埋在半导体本体（11）中的电绝缘区域（26,27）形成该收缩部）。根据本发明，形成在掩埋电绝缘区域（26,27）上方的半导体本体的一部分是单晶的。这使得器件的强大的侧向小型化并且导致晶体管的优异的高频特性。由于通过根据本发明的制造方法的制造，这种装置（10）是可能的。

3. 发明授权

US07906403B2 Bipolar transistor and method of fabricating the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07906403B2
公开(公告)日：2011-03-15
申请号：US11814281
申请日：2006-01-12
申请人： Johannes JTM Donkers , Wibo D. Van Noort , Philippe Meunier-Beillard , Sebastien Nuttinck , Erwin Hujzen , Francois Neuilly
发明人： Johannes JTM Donkers , Wibo D. Van Noort , Philippe Meunier-Beillard , Sebastien Nuttinck , Erwin Hujzen , Francois Neuilly
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.
摘要翻译：与示例实施例一致，存在集成在标准CMOS浅沟槽隔离区的沟槽中的集电极串联电阻减小的双极晶体管。双极晶体管包括在一个制造步骤中制造的集电极区域，因此具有较短的集电极串联电阻的导电路径，从而改善了双极晶体管的高频性能。所述双极晶体管还包括基极区域，所述基极区域在所述沟槽的底部上的所述集电极区域（6,34）的选定部分上具有第一部分，并且所述基极的所述第一部分的选定部分上的发射极区域地区。基极触点与绝缘区域上的基极区域的第二部分上的基极区域电接触。集电极区域在突出部的顶部与集电极触点电接触。

4. 发明申请

US20100022056A1 METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US20100022056A1
公开(公告)日：2010-01-28
申请号：US12439363
申请日：2007-08-29
申请人： Johannes J. T. M. Donkers , Sebastien Nuttinck , Guillaume L. R. Boccardi , Francois Neuilly
发明人： Johannes J. T. M. Donkers , Sebastien Nuttinck , Guillaume L. R. Boccardi , Francois Neuilly
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/407 , H01L29/66242
摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.
摘要翻译：本发明提供了制造双极晶体管的替代和较不复杂的方法，其包括在与集电极区域（21）相邻的沟槽（7）中的场板（17），该场板（17）采用减小的表面场（Resurf ）效果。 Resurf效应重塑了集电极区域（21）中的电场分布，使得对于相同的集电极 - 基极击穿电压，可以有效地增加集电极区域（21）的掺杂浓度，从而降低集电极电阻，从而增加双极性晶体管速度。该方法包括在第一基层（4）中形成基窗（6）从而暴露集电区（21）的顶表面和隔离区（3）的一部分的步骤。通过去除隔离区域（3）的露出部分形成沟槽（7），之后隔离层（9,10）形成在沟槽（7）的表面上。在隔离层（10）上形成第二基层（13），从而在集电区域（21）的顶面上形成场板（17），从而形成基极区域（31）从而在第一基底层（4），基底区域（31）和场板（17）之间形成电连接。在基极区域（31）的顶部形成发射极区域（41），从而形成Resurf双极型晶体管。

5. 发明授权

US08026146B2 Method of manufacturing a bipolar transistor 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US08026146B2
公开(公告)日：2011-09-27
申请号：US12439363
申请日：2007-08-29
申请人： Johannes J. T. M. Donkers , Sebastien Nuttinck , Guillaume L. R. Boccardi , Francois Neuilly
发明人： Johannes J. T. M. Donkers , Sebastien Nuttinck , Guillaume L. R. Boccardi , Francois Neuilly
IPC分类号： H01L21/8222
CPC分类号： H01L29/7378 , H01L29/407 , H01L29/66242
摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.
摘要翻译：本发明提供了制造双极晶体管的替代和较不复杂的方法，其包括在与集电极区域（21）相邻的沟槽（7）中的场板（17），该场板（17）采用减小的表面场（Resurf ）效果。 Resurf效应重塑了集电极区域（21）中的电场分布，使得对于相同的集电极 - 基极击穿电压，可以有效地增加集电极区域（21）的掺杂浓度，从而降低集电极电阻，从而增加双极性晶体管速度。该方法包括在第一基层（4）中形成基窗（6）从而暴露集电区（21）的顶表面和隔离区（3）的一部分的步骤。通过去除隔离区域（3）的露出部分形成沟槽（7），之后隔离层（9,10）形成在沟槽（7）的表面上。在隔离层（10）上形成第二基层（13），从而在集电区域（21）的顶面上形成场板（17），从而形成基极区域（31）从而在第一基底层（4），基底区域（31）和场板（17）之间形成电连接。在基极区域（31）的顶部形成发射极区域（41），从而形成Resurf双极型晶体管。

6. 发明授权

US07605027B2 Method of fabricating a bipolar transistor 失效
标题翻译：制造双极晶体管的方法
公开(公告)号：US07605027B2
公开(公告)日：2009-10-20
申请号：US11913049
申请日：2006-04-24
申请人： Philippe Meunier-Beillard , Erwin Hijzen , Johannes J. T. M. Donkers , Francois Neuilly
发明人： Philippe Meunier-Beillard , Erwin Hijzen , Johannes J. T. M. Donkers , Francois Neuilly
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66272 , H01L29/0821
摘要： A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.
摘要翻译：公开了在第一沟槽（11）中制造双极晶体管的方法，其中仅施加一个形成第一沟槽（11）和第二沟槽（12）的光刻掩模。集电极区域（21）在第一沟槽（11）和第二沟槽（12）中自对准地形成。基部区域（31）在位于第一沟槽（11）中的集电极区域（21）的一部分上自对准地形成。发射极区域（41）在基极区域（31）的一部分上自对准地形成。在所述第二沟槽（12）中形成与所述集电极区域（21）的接触，并且在所述第一沟槽（11）中形成与所述基部区域（31）的接触。双极晶体管的制造可以集成在标准CMOS工艺中。

7. 发明申请

US20110001217A1 ULTRA HIGH DENSITY CAPACITY COMPRISING PILLAR-SHAPED CAPACITORS FORMED ON BOTH SIDES OF A SUBSTRATE 有权
标题翻译：超高密度容量包含形成在基板两面上的支柱形电容器
公开(公告)号：US20110001217A1
公开(公告)日：2011-01-06
申请号：US12918773
申请日：2009-02-17
申请人： Francois Neuilly , Francois Le Cornec
发明人： Francois Neuilly , Francois Le Cornec
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L23/49827 , H01L27/0207 , H01L28/92 , H01L29/66181 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940). Via connections (920) are provided in trenches that go through the whole thickness of the wafer.
摘要翻译：本发明通过使用两个晶片侧面描述了集成在半导体衬底中，优选为Si衬底的超高密度电容器设计。电容器是柱状的并且包括由电介质层（940）分开的电极（930,950）。通过连接（920）设置在穿过晶片的整个厚度的沟槽中。

8. 发明申请

US20110101531A1 THERMO-MECHANICAL STRESS IN SEMICONDUCTOR WAFERS 审中-公开
标题翻译：半导体器件中的机械应力
公开(公告)号：US20110101531A1
公开(公告)日：2011-05-05
申请号：US12995441
申请日：2009-05-21
申请人： Francois Neuilly , Paul Messaoudi
发明人： Francois Neuilly , Paul Messaoudi
IPC分类号： H01L23/532 , H01L23/52 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76838 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05571 , H01L2224/05684 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014
摘要： An apparatus for restricting the thermo-mechanical stress in semiconductor wafers both during manufacture, and during the operating lifetime of the semiconductor devices and systems formed on the wafer. An electrically conductive track 8 can be formed with a stopper 16 which can be positioned at least at one end of the electrically conductive track 8. The differential expansion during heating of electrically conductive tracks 8 with respect to a semiconductor wafer 4 can be restricted by the stopper 16.
摘要翻译：一种用于在制造期间和在晶片上形成的半导体器件和系统的工作寿命期间限制半导体晶片中的热机械应力的装置。导电轨道8可以形成有止动器16，止动件16可以位于导电轨道8的至少一端。导电轨道8相对于半导体晶片4的加热期间的差动膨胀可以通过塞16。

9. 发明申请

US20080272427A1 Sonos Memory Device With Reduced Short-Channel Effects 有权
标题翻译： Sonos内存设备，减少短信道效应
公开(公告)号：US20080272427A1
公开(公告)日：2008-11-06
申请号：US12158131
申请日：2006-12-18
申请人： Robertus T.F. Van Schaijk , Francois Neuilly , Michiel J. Van Duuren
发明人： Robertus T.F. Van Schaijk , Francois Neuilly , Michiel J. Van Duuren
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42392 , B82Y10/00 , G11C16/0466 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/66833 , H01L29/785 , H01L29/792 , H01L29/7923
摘要： A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer (2) comprises a source region (12,S), a drain region (12,D), a channel region (CO), a memory element (ME), and a gate (G). The channel region (CO) extends in a first direction (X) between the source region (12,S) and the drain region (12,D). The gate (G) is disposed near the channel region (CO) and the memory element (ME) is disposed in between the channel region (CO) and the gate. The channel region is disposed within a beam-shaped semiconductor layer (4), with the beam-shaped semiconductor layer (4a, 4b, 4c, 4d) extending in the first direction (X) between the source (12,S) and drain (12,D) regions and having lateral surfaces (4a, 4b, 4c, 4d) extending parallel to the first direction (X). The memory element comprises a charge-trapping stack (8) which covers of the lateral surfaces at least the lower surface (4c) directed towards the semiconductor surface layer (2) and the side surfaces (4b, 4d) which are directly connecting to the lower surface (4c) so as to embed the beam-shaped semiconductor layer (4) in a U-shaped form of the charge trapping stack (8).
摘要翻译：具有半导体表面层（2）的半导体衬底上的非易失性存储器件包括源极区（12，S），漏极区（12），沟道区（CO），存储元件（ME），和门（G）。沟道区域（CO）在源极区域（12）与漏极区域（12）之间的第一方向（X）上延伸。栅极（G）设置在沟道区域（CO）附近，存储元件（ME）设置在沟道区域（CO）和栅极之间。所述通道区域设置在波束形半导体层（4）内，所述波束形半导体层（4a，4b，4c，4d）沿着所述源极（12， S）和漏极（12，D）区域并且具有平行于第一方向（X）延伸的侧表面（4a，4b，4c，4c）。存储元件包括电荷俘获堆叠（8），其至少覆盖指向半导体表面层（2）的下表面（4c）和侧表面（4b，4d）的侧表面，其直接连接到下表面（4c），以将束形半导体层（4）嵌入U形形式的电荷捕获堆叠（8）中。

10. 发明授权

US08525250B2 SONOS memory device with reduced short-channel effects 有权
标题翻译： SONOS存储器件具有减少的短通道效应
公开(公告)号：US08525250B2
公开(公告)日：2013-09-03
申请号：US12158131
申请日：2006-12-18
申请人： Robertus T. F. Van Schaijk , Francois Neuilly , Michiel J. Van Duuren
发明人： Robertus T. F. Van Schaijk , Francois Neuilly , Michiel J. Van Duuren
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/42392 , B82Y10/00 , G11C16/0466 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/66833 , H01L29/785 , H01L29/792 , H01L29/7923
摘要： According to certain embodiments, a non-volatile memory device on a semiconductor substrate having a semiconductor surface layer comprises a channel region that extends in a first direction between the source and drain regions. The gate is disposed near the channel region and the memory element is disposed in between the channel region and the gate. The channel region is disposed within a beam-shaped semiconductor layer, with the beam-shaped semiconductor layer extending in the first direction between the source and drain regions and having lateral surfaces extending parallel to the first direction. The memory element comprises a charge-trapping stack so as to embed therein the beam-shaped semiconductor layer in a U-shaped form.
摘要翻译：根据某些实施例，具有半导体表面层的半导体衬底上的非易失性存储器件包括在源区和漏区之间沿第一方向延伸的沟道区。栅极设置在沟道区附近，并且存储元件设置在沟道区域和栅极之间。沟道区域设置在波束形半导体层内，其中波束形半导体层在源极和漏极区域之间沿第一方向延伸并且具有平行于第一方向延伸的侧表面。存储元件包括电荷俘获堆叠，以将其中的束状半导体层嵌入U形形式中。

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