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1. 发明授权

US08346527B2 Simulating an operation of a digital circuit 有权
标题翻译：模拟数字电路的操作
公开(公告)号：US08346527B2
公开(公告)日：2013-01-01
申请号：US12351201
申请日：2009-01-09
申请人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
发明人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).
摘要翻译：描述用于模拟数字电路（01）的操作的方法。该方法利用循环模拟，其中在数字电路（01）的基于循环的仿真模型（34）中，数字电路（01）的组件（02,03,04,05）在一个周期（19）功能时钟（Clk）。根据本发明，通过将延迟锁存器（15,16,17）插入到基于循环的仿真模型（34）中，实际数字电路（01）即芯片或组合逻辑（01））定时信息被包括在循环模拟中数字电路（01），其中使用非功能时钟（Sim时钟）对延迟锁存器（15,16,17）进行时钟，使得每个延迟锁存器（15,16,17）延迟信号的传播（I，J，K）通过非功能时钟（Sim时钟）的周期（20）。

2. 发明申请

US20090182545A1 Simulating an Operation of a Digital Circuit 有权
标题翻译：模拟数字电路的操作
公开(公告)号：US20090182545A1
公开(公告)日：2009-07-16
申请号：US12351201
申请日：2009-01-09
申请人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
发明人： Joerg Walter , Lothar Felten , Volker Urban , Norbert Schumacher , Marcel Naggatz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).
摘要翻译：描述用于模拟数字电路（01）的操作的方法。该方法利用循环模拟，其中在数字电路（01）的基于循环的仿真模型（34）中，数字电路（01）的组件（02,03,04,05）在一个周期（19）功能时钟（Clk）。根据本发明，通过将延迟锁存器（15,16,17）插入到基于循环的仿真模型（34）中，实际数字电路（01）即芯片或组合逻辑（01））定时信息被包括在循环模拟中数字电路（01），其中使用非功能时钟（Sim时钟）对延迟锁存器（15,16,17）进行时钟，使得每个延迟锁存器（15,16,17）延迟信号的传播（I，J，K）通过非功能时钟（Sim时钟）的周期（20）。

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