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1. 发明授权

US07877649B2 Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs 有权
标题翻译：用于使用用于多个输入和输出的公共节点来测试存储器芯片的方法和装置
公开(公告)号：US07877649B2
公开(公告)日：2011-01-25
申请号：US11934644
申请日：2007-11-02
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
摘要翻译：提供一种用于测试包括存储器的测试装置的集成装置的装置和方法。存储器的至少两个数据输入耦合到测试设备的数据输出。作为替代，存储器的至少两个数据输出耦合到测试设备的数据输入。测试数据从测试设备传输到存储器芯片并写入存储器的存储单元。从存储器的存储单元读取数据并从存储器传送到测试设备。将从存储器芯片读取的数据与写入存储器的测试数据进行比较，以识别存储器的故障。

2. 发明申请

US20080141075A1 METHOD AND APPARATUS FOR TESTING A MEMORY CHIP 有权
标题翻译：用于测试记忆芯片的方法和装置
公开(公告)号：US20080141075A1
公开(公告)日：2008-06-12
申请号：US11934644
申请日：2007-11-02
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
IPC分类号： G06F11/00 , G06F11/07 , G11C7/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
摘要翻译：提供一种用于测试包括存储器的测试装置的集成装置的装置和方法。存储器的至少两个数据输入耦合到测试设备的数据输出。作为替代，存储器的至少两个数据输出耦合到测试设备的数据输入。测试数据从测试设备传输到存储器芯片并写入存储器的存储单元。从存储器的存储单元读取数据并从存储器传送到测试设备。将从存储器芯片读取的数据与写入存储器的测试数据进行比较，以识别存储器的故障。

3. 发明申请

US20060192085A1 Semiconductor circuit and arrangement and method for monitoring fuses of a semiconductor circuit 审中-公开
标题翻译：用于监测半导体电路的熔丝的半导体电路及其布置方法
公开(公告)号：US20060192085A1
公开(公告)日：2006-08-31
申请号：US11341904
申请日：2006-01-27
申请人： Georg Eggers , Manfred Proell , Joerg Kliewer , Stephan Schroeder
发明人： Georg Eggers , Manfred Proell , Joerg Kliewer , Stephan Schroeder
IPC分类号： H01L31/00
CPC分类号： H01L27/112 , H01L23/5258 , H01L27/105 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit comprises a fuse and a photoelement. A conduction layer of the fuse at least partly shades a photosensor region of the photoelement from a light bundle falling onto the semiconductor circuit. An arrangement for electro-optical monitoring of fuses of a semiconductor circuit additionally comprises an illumination device for generating the light bundle and a measuring device connected to two of the terminal contacts of the semiconductor circuit. In a method for the electro-optical monitoring of fuses of a semiconductor circuit a measuring device is connected to two of the terminal contacts and the semiconductor circuit is illuminated with a light bundle.
摘要翻译：半导体电路包括保险丝和光电元件。熔丝的导电层至少部分地将光电元件的光电传感器区域从落在半导体电路上的光束遮蔽。用于半导体电路的熔丝的电光监视的装置还包括用于产生光束的照明装置和连接到半导体电路的两个端子触点的测量装置。在半导体电路的保险丝的电光监测方法中，测量装置连接到两个端子触点，半导体电路用光束照射。

4. 发明申请

US20070260955A1 TEST AUXILIARY DEVICE IN A MEMORY MODULE 审中-公开
标题翻译：在存储器模块中测试辅助设备
公开(公告)号：US20070260955A1
公开(公告)日：2007-11-08
申请号：US11677572
申请日：2007-02-21
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
IPC分类号： G01R31/28
CPC分类号： G11C29/36 , G11C2029/3602
摘要： Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.
摘要翻译：将测试图案应用于存储器模块中的单元的方法和装置。存储器模块中的测试辅助设备包含用于从至少两个基本M位测试模式中选择测试模式的测试模式选择设备。测试图案被应用于存储器模块的M组数据线，M是整数。

5. 发明申请

US20050280036A1 Semiconductor product having a first and at least one further semiconductor circuit and method 审中-公开
标题翻译：具有第一和至少一个半导体电路和方法的半导体产品
公开(公告)号：US20050280036A1
公开(公告)日：2005-12-22
申请号：US11146305
申请日：2005-06-06
申请人： Stephan Schroeder , Manfred Proell , Arndt Gruber , Georg Eggers
发明人： Stephan Schroeder , Manfred Proell , Arndt Gruber , Georg Eggers
IPC分类号： G11C5/06 , G11C7/10 , G11C29/00 , H01L21/66 , H01L23/31 , H01L23/50 , H01L23/538 , H01L23/544 , H01L25/065 , H01L27/10 , H01L27/105
CPC分类号： H01L25/0655 , H01L23/3128 , H01L23/5389 , H01L24/24 , H01L27/105 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A semiconductor product includes a first semiconductor circuit and at least one further integrated semiconductor circuit arranged together on a semiconductor substrate. The first semiconductor circuit and the at least one further semiconductor circuit are separated from one another by a frame region and each including contact connections. Interconnects cross the frame region and short-circuit a contact connection of the first semiconductor circuit with a contact connection of the at least one further semiconductor circuit.
摘要翻译：半导体产品包括第一半导体电路和一起布置在半导体衬底上的至少一个另外的集成半导体电路。第一半导体电路和至少一个另外的半导体电路通过框架区域彼此分开，并且每个包括接触连接。互连件穿过框架区域并使第一半导体电路的接触连接与至少一个另外的半导体电路的接触连接短路。

6. 发明申请

US20060193168A1 Integrated semiconductor memory and method for operating a semiconductor memory 失效
标题翻译：用于操作半导体存储器的集成半导体存储器和方法
公开(公告)号：US20060193168A1
公开(公告)日：2006-08-31
申请号：US11331365
申请日：2006-01-13
申请人： Stephan Schroder , Herbert Benzinger , Georg Eggers , Manfred Proll , Jorg Kliewer
发明人： Stephan Schroder , Herbert Benzinger , Georg Eggers , Manfred Proll , Jorg Kliewer
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/404 , H01L27/10885
摘要： An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor. The resultant increase in the signal strength makes the semiconductor memory insensitive toward signal corruptions which arise for example in the case of operating voltages at different levels for selection transistors and for transistors in the signal amplifier.
摘要翻译：集成半导体存储器件包括各自具有选择晶体管和存储电容器的存储单元。这种类型的存储单元通常通过读出放大器中与存储器单元连接的位线的电位进行读取，其中互补的第二位线的电位和识别的电压差被放大。根据本发明的半导体存储器提供了未连接到选择晶体管以连接到互补的第二位线的电容器电极。结果，对于具有相同幅度的工作电压，由于现在由读出放大器输出的两个相互扩展的电位用于偏置存储电容器，所以可以将大量的电荷存储在存储电容器中。信号强度的增加使得半导体存储器对信号损坏不敏感，例如在用于选择晶体管的不同电平的操作电压和信号放大器中的晶体管的情况下。

7. 发明申请

US20050057988A1 Method and device for testing semiconductor memory devices 有权
标题翻译：用于测试半导体存储器件的方法和装置
公开(公告)号：US20050057988A1
公开(公告)日：2005-03-17
申请号：US10487255
申请日：2002-08-21
申请人： Eric Cordes , Christian Stocken , Georg Eggers , Jens Luepke
发明人： Eric Cordes , Christian Stocken , Georg Eggers , Jens Luepke
IPC分类号： G01R31/28 , G11C7/10 , G11C11/401 , G11C29/50 , G11C29/56 , G11C7/00
CPC分类号： G11C29/50012 , G11C7/1051 , G11C7/1087 , G11C11/401 , G11C29/50
摘要： A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.
摘要翻译：一种用于半导体存储器件的测试方法，具有用于数据选通信号的双向数据选通端子，并且在测试装置处具有用于数据信号的至少一个数据端，其至少可以产生数据选通和数据信号，评估数据信号。存储器件连接到产生数据选通和数据信号的测试装置，并传送和评估数据信号。在使用数据选通和数据信号的测试过程中，数据从第一半导体存储器件传送到相同类型的第二半导体存储器件，并且在通过测试装置从第二半导体存储器件读出之后被评估。

8. 发明申请

US20070176255A1 Integrated circuit arrangement 审中-公开
标题翻译：集成电路布置
公开(公告)号：US20070176255A1
公开(公告)日：2007-08-02
申请号：US11344960
申请日：2006-01-31
申请人： Franz Kreupl , Georg Eggers , Herbert Benzinger , Ingo Bormann , Martin Schnell
发明人： Franz Kreupl , Georg Eggers , Herbert Benzinger , Ingo Bormann , Martin Schnell
IPC分类号： H01L29/00
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/025 , G11C17/16 , G11C2213/16 , H01L23/5258 , H01L29/0673 , H01L51/0048 , H01L51/0545 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement comprises at least one one-time programmable storage element, which can be electrically deactivated, having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire.
摘要翻译：集成电路装置包括至少一个可以被电去激活的一次性可编程存储元件，其具有至少一个导电或半导电纳米管或至少一个导电或半导电纳米线。

9. 发明申请

US20050194614A1 Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory 失效
标题翻译：集成半导体存储器和用于电应力集成半导体存储器的方法
公开(公告)号：US20050194614A1
公开(公告)日：2005-09-08
申请号：US11061087
申请日：2005-02-18
申请人： Georg Eggers , Stephan Schroder , Manfred Proll , Herbert Benzinger
发明人： Georg Eggers , Stephan Schroder , Manfred Proll , Herbert Benzinger
IPC分类号： G11C11/407 , G11C29/00 , G11C29/02 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L29/73 , H01L29/739 , H01L29/74
CPC分类号： G11C29/025 , G11C29/02 , H01L27/105 , H01L27/10891
摘要： Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.
摘要翻译：半导体存储器（1）具有分段字线（5a，5b），其在每种情况下具有由导电金属制成的主字线（10a，10b）和多个互连片段（15a，15b）），其耦合到主字线（10a，10b），其通过至少一个接触孔填充物（11）在每种情况下耦合到相应的主字线（10a，10b）。如果接触孔填充物（11）中的一个有缺陷或高电阻，则会发生半导体存储器的功能错误。两个相应字线（5a，5b）的互连段（15a，5b）可以借助于开关单元（20）成对地短路，由此通过接触孔填充物（11）可以用于电接触接触孔填充物（11）。因此，分段字线的接触孔填充的电应力成为可能。

10. 发明授权

US07247956B2 Performance test board 有权
标题翻译：性能测试板
公开(公告)号：US07247956B2
公开(公告)日：2007-07-24
申请号：US11000252
申请日：2004-11-30
申请人： Hartmut Berger , Kapil Gupta , Georg Eggers , Claus Peter , Hans-Joachim Kremer
发明人： Hartmut Berger , Kapil Gupta , Georg Eggers , Claus Peter , Hans-Joachim Kremer
IPC分类号： G01R31/00
CPC分类号： G01R31/31924
摘要： Performance Test Board for connecting at least one device under test (DUT) to a test system which has internal power supply sources (IPS) wherein said Performance Test Board (PTB) comprises at least one DC-DC-converter having an input terminal to which several internal power supply sources of said test system are connected in parallel, an output terminal to which a power supply terminal of said device under test (DUT) is connected and a control terminal to which a further internal power supply source of said test system is connected.
摘要翻译：用于将至少一个被测设备（DUT）连接到具有内部电源（IPS）的测试系统的性能测试板，其中所述性能测试板（PTB）包括至少一个具有输入端子的DC-DC转换器，所述测试系统的几个内部电源源并联连接，连接被测设备（DUT）的电源端子的输出端子和所述测试系统的另一个内部电源供给的控制端子连接的。

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