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1. 发明申请

US20070070758A1 SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER AND SWITCH 审中-公开
标题翻译：具有感应放大器和开关的半导体存储器
公开(公告)号：US20070070758A1
公开(公告)日：2007-03-29
申请号：US11534400
申请日：2006-09-22
申请人： Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
发明人： Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C8/10 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed. The means is, during the switching of the sense amplifier to the line, placed in a conductive state for a differently long time and/or differently strongly, depending on the respective operating mode of the semiconductor memory.
摘要翻译：公开了一种使用至少一个读出放大器和用于将读出放大器切换至至少一条线路的装置来操作半导体存储器和半导体存储器的方法。这意味着，根据半导体存储器的相应工作模式，在感测放大器切换到线路期间，其处于不同长时间和/或不同程度的导通状态。

2. 发明授权

US07120074B2 Semiconductor memory and method for operating a semiconductor memory 有权
标题翻译：用于操作半导体存储器的半导体存储器和方法
公开(公告)号：US07120074B2
公开(公告)日：2006-10-10
申请号：US10911230
申请日：2004-08-04
申请人： Manfred Proell , Herbert Benzinger , Manfred Dobler , Joerg Kliewer
发明人： Manfred Proell , Herbert Benzinger , Manfred Dobler , Joerg Kliewer
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C8/08 , G11C11/406 , G11C11/4085 , G11C2211/4068
摘要： A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.
摘要翻译：半导体存储器包括具有存储电容器的存储单元（2）和具有电极的晶体管，该电极可与两个不同的电位（V 1，V 2）电偏置，以便打开和闭合晶体管。用于晶体管截止状态的电极电位（V 2）是依赖于温度的温度的电位，其值由半导体存储器（1）温度控制，使得第二电位（V 2）变得更大与温度（T）增加时不同于第一电位（V 1）。

3. 发明申请

US20060192085A1 Semiconductor circuit and arrangement and method for monitoring fuses of a semiconductor circuit 审中-公开
标题翻译：用于监测半导体电路的熔丝的半导体电路及其布置方法
公开(公告)号：US20060192085A1
公开(公告)日：2006-08-31
申请号：US11341904
申请日：2006-01-27
申请人： Georg Eggers , Manfred Proell , Joerg Kliewer , Stephan Schroeder
发明人： Georg Eggers , Manfred Proell , Joerg Kliewer , Stephan Schroeder
IPC分类号： H01L31/00
CPC分类号： H01L27/112 , H01L23/5258 , H01L27/105 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit comprises a fuse and a photoelement. A conduction layer of the fuse at least partly shades a photosensor region of the photoelement from a light bundle falling onto the semiconductor circuit. An arrangement for electro-optical monitoring of fuses of a semiconductor circuit additionally comprises an illumination device for generating the light bundle and a measuring device connected to two of the terminal contacts of the semiconductor circuit. In a method for the electro-optical monitoring of fuses of a semiconductor circuit a measuring device is connected to two of the terminal contacts and the semiconductor circuit is illuminated with a light bundle.
摘要翻译：半导体电路包括保险丝和光电元件。熔丝的导电层至少部分地将光电元件的光电传感器区域从落在半导体电路上的光束遮蔽。用于半导体电路的熔丝的电光监视的装置还包括用于产生光束的照明装置和连接到半导体电路的两个端子触点的测量装置。在半导体电路的保险丝的电光监测方法中，测量装置连接到两个端子触点，半导体电路用光束照射。

4. 发明申请

US20080205173A1 Method and System for Testing an Integrated Circuit 失效
标题翻译：集成电路测试方法和系统
公开(公告)号：US20080205173A1
公开(公告)日：2008-08-28
申请号：US12022422
申请日：2008-01-30
申请人： Joerg Kliewer , Klaus Nierle , Martin Versen
发明人： Joerg Kliewer , Klaus Nierle , Martin Versen
IPC分类号： G01R31/02 , G01R31/3187 , G11C29/00
CPC分类号： G01R31/3004
摘要： An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.
摘要翻译：一种集成电路，包括：a）至少一个集成电压发生器，用于为相关联的集成负载产生低电压; b）连接到所述电压发生器的集成电压发生器测试逻辑，所述电压发生器在作为所述集成电压发生器的操作状态的测试操作模式中，所述电压发生器测试逻辑根据外部控制信号而在有效工作状态和待机操作状态 c）用于将所述产生的负载电压切换到所述集成负载的内部负载开关，所述内部负载开关可通过内部控制信号来控制; d）其中所述测试操作模式中的所述电压发生器测试逻辑独立于相关联的内部控制切换信号切换所述集成电压发生器的操作状态，以设置施加到该负载的所述负载电压的时间电压分布。

5. 发明申请

US20080141075A1 METHOD AND APPARATUS FOR TESTING A MEMORY CHIP 有权
标题翻译：用于测试记忆芯片的方法和装置
公开(公告)号：US20080141075A1
公开(公告)日：2008-06-12
申请号：US11934644
申请日：2007-11-02
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
IPC分类号： G06F11/00 , G06F11/07 , G11C7/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
摘要翻译：提供一种用于测试包括存储器的测试装置的集成装置的装置和方法。存储器的至少两个数据输入耦合到测试设备的数据输出。作为替代，存储器的至少两个数据输出耦合到测试设备的数据输入。测试数据从测试设备传输到存储器芯片并写入存储器的存储单元。从存储器的存储单元读取数据并从存储器传送到测试设备。将从存储器芯片读取的数据与写入存储器的测试数据进行比较，以识别存储器的故障。

6. 发明授权

US07206238B2 Integrated semiconductor memory comprising at least one word line and method 有权
标题翻译：集成半导体存储器，包括至少一个字线和方法
公开(公告)号：US07206238B2
公开(公告)日：2007-04-17
申请号：US11218913
申请日：2005-09-01
申请人： Joerg Kliewer , Herbert Benzinger , Stephan Schroeder , Manfred Proell
发明人： Joerg Kliewer , Herbert Benzinger , Stephan Schroeder , Manfred Proell
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.
摘要翻译：半导体存储器和测试方法，用于在激活操作或去激活操作之后测试字线段（12）是否浮动。为此，在字线段（12）发生电荷反转的情况下发生的充电反转电流（I）或馈送到字线（12）或导出的电荷量（Q）由字线段（12）作为测量结果。如果在字线段（12）激活或去激活时，测量的电荷反转电流（I）或相应的电荷量（Q）小于下限值，则确定相关字线段（ 12）有接触端子不良。以这种方式，由此可以识别高阻抗或有缺陷的接触孔填充，并且可以用冗余字线替换相关联的字线段（12）。

7. 发明申请

US20070047355A1 METHOD FOR DETECTING A LEAKAGE CURRENT OF A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于检测半导体存储器的泄漏电流的方法
公开(公告)号：US20070047355A1
公开(公告)日：2007-03-01
申请号：US11467740
申请日：2006-08-28
申请人： Herbert Benzinger , Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
发明人： Herbert Benzinger , Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/02
CPC分类号： G11C11/4078 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C29/02 , G11C2029/1204 , G11C2029/5006 , G11C2207/005
摘要： A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.
摘要翻译：公开了一种用于检测半导体存储器的位线中的漏电流的方法。在一个实施例中，该方法包括经由隔离晶体管将读出放大器与位线的连接隔离，将存储器单元读出到位线，等待直到经过预定的延迟时间，使得漏电流可测量地改变延迟时间内位线上的电压。读出放大器通过隔离晶体管与位线短路。位线上的电压由读出放大器收集，并与参考电压进行比较，以便检测漏电流。

8. 发明授权

US06906972B2 Integrated DRAM semiconductor memory and method for operating the same 失效
标题翻译：集成DRAM半导体存储器及其操作方法
公开(公告)号：US06906972B2
公开(公告)日：2005-06-14
申请号：US10733332
申请日：2003-12-12
申请人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
发明人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
IPC分类号： G11C7/10 , G11C11/4091 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C11/4091 , G11C11/4096 , G11C2207/002
摘要： An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.
摘要翻译：集成半导体存储器和用于操作具有在列方向（Y）上分割的本地数据线（LDQT，LDQC）的这种存储器，特别是DRAM存储器的方法，该本地数据线可以通过CSL开关作为响应来连接到通过在行方向（X）上运行的CSL线（CSL）馈送到主感测放大器的列选择信号，用于向或从相应段（I，II，III）的位线传送或接收扩展数据信号，交换机被布置在本地数据线（LDQT，LDQC）的相邻段之间的接口处，用于连接到相邻段（I，II，III）的本地数据线（LDQT，LDQC）。取决于分别馈送到每个所述LDQ开关的控制信号的LDQ开关在至少两个相邻的LDQ段之间的每个读取周期之前的预充电阶段期间被关闭。

9. 发明申请

US20070260955A1 TEST AUXILIARY DEVICE IN A MEMORY MODULE 审中-公开
标题翻译：在存储器模块中测试辅助设备
公开(公告)号：US20070260955A1
公开(公告)日：2007-11-08
申请号：US11677572
申请日：2007-02-21
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
IPC分类号： G01R31/28
CPC分类号： G11C29/36 , G11C2029/3602
摘要： Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.
摘要翻译：将测试图案应用于存储器模块中的单元的方法和装置。存储器模块中的测试辅助设备包含用于从至少两个基本M位测试模式中选择测试模式的测试模式选择设备。测试图案被应用于存储器模块的M组数据线，M是整数。

10. 发明授权

US07110310B2 RAM store and control method therefor 有权
标题翻译： RAM存储及其控制方法
公开(公告)号：US07110310B2
公开(公告)日：2006-09-19
申请号：US10762280
申请日：2004-01-23
申请人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
发明人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
IPC分类号： E03D1/02
CPC分类号： G11C7/18 , G11C7/12 , G11C11/4094 , G11C11/4097 , G11C2207/12
摘要： The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21–24) from the adjacent cell blocks and the bit line pairs (21, 22; 21–24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21–24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21–24) which are in the precharge phase to one another. The shorting transistor (30) is arranged in or on the respective sense amplifier (SA) jointly for all bit line pairs (21, 22; 21–24) which can be connected to a repetitive sense amplifier (SA), and it can be switched by a separate shorting control signal (EQLx) via a dedicated control line (9).
摘要翻译：本发明涉及具有共享SA结构的RAM存储器，其中布置在两个相邻相邻单元块之间的SA带（10）中的读出放大器（SA）被多个位线对（21,22; 21-24 ）和位线对（21,22; 21-24）具有分别与它们相关联的电荷均衡电路，用于在位线对（21,22）的位线半部之间执行电荷均衡 ; 21-24），其中提供短路晶体管（30），当短路晶体管（30）由控制信号（EQLx）提示时，连接位线对（21,22）的位线半部（BLT，BLC） ; 21-24），它们彼此处于预充电阶段。短路晶体管（30）对于可以连接到重复读出放大器（SA）的所有位线对（21,22; 21-24）共同布置在相应的读出放大器（SA）中或上，通过专用控制线（9）通过单独的短路控制信号（EQLx）进行切换。

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