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1. 发明授权

US08151085B2 Method for address translation in virtual machines 失效
标题翻译：虚拟机地址转换方法
公开(公告)号：US08151085B2
公开(公告)日：2012-04-03
申请号：US12353478
申请日：2009-01-14
申请人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
发明人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/0888 , G06F2009/45583
摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
摘要翻译：本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

2. 发明申请

US20090187731A1 Method for Address Translation in Virtual Machines 失效
标题翻译：虚拟机地址转换方法
公开(公告)号：US20090187731A1
公开(公告)日：2009-07-23
申请号：US12353478
申请日：2009-01-14
申请人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
发明人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
IPC分类号： G06F12/10 , G06F9/455
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/0888 , G06F2009/45583
摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
摘要翻译：本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

3. 发明授权

US08117574B2 Implementing a serialization construct within an environment of parallel data flow graphs 有权
标题翻译：在并行数据流图的环境中实现序列化构造
公开(公告)号：US08117574B2
公开(公告)日：2012-02-14
申请号：US12330890
申请日：2008-12-09
申请人： Joerg Deutschle , Harald Gerst , Joerg Walter
发明人： Joerg Deutschle , Harald Gerst , Joerg Walter
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F11/3684 , G01R31/31813 , G01R31/318371
摘要： A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated.
摘要翻译：序列化构造在多个并行数据流图的环境中实现。静态节点附加到每个活动数据流图。停顿节点在活动数据流图的执行完成之前防止令牌传递到链中的下一个数据流图。实现串行数据流图，以提供串行执行，而没有其他数据流图是活动的。序列化节点附加到串行数据流图的起始点。序列化结束节点附加到串行数据流图的端点。串行化节点被激活以开始串行操作。序列化结束节点在串行操作终止后被激活。

4. 发明授权

US09015025B2 Verifying processor-sparing functionality in a simulation environment 有权
公开(公告)号：US09015025B2
公开(公告)日：2015-04-21
申请号：US13285460
申请日：2011-10-31
申请人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
发明人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
IPC分类号： G06F17/50 , G06F11/22 , G06F11/20
CPC分类号： G06F17/5009 , G06F11/202 , G06F11/2242 , G06F17/5022 , G06F2217/68
摘要： A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

5. 发明申请

US20090070717A1 Method and System for Generating Coverage Data for a Switch Frequency of HDL or VHDL Signals 有权
标题翻译：用于生成HDL或VHDL信号的开关频率的覆盖数据的方法和系统
公开(公告)号：US20090070717A1
公开(公告)日：2009-03-12
申请号：US12205476
申请日：2008-09-05
申请人： Joerg Deutschle , Lothar Felten , Ursel Hahn , Klaus Keuerleber
发明人： Joerg Deutschle , Lothar Felten , Ursel Hahn , Klaus Keuerleber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318364 , G06F17/505
摘要： The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model (10) within a register transfer level, providing a filtering algorithm or filtering rules (12) for signals occurring in the HDL or VHDL hardware description model (10), extracting signals from the HDL or VHDL hardware description model (10) according to said filtering algorithm or filtering rules (12) in order to get relevant signals, performing a simulation process (18) of the HDL or VHDL hardware description model (10), performing a checking routine (20) for the relevant signals in every cycle and storing and/or cumulating the relevant signals in a data base (22). Further the present invention relates to a corresponding system.
摘要翻译：本发明涉及一种用于产生HDL或VHDL信号的切换频率的覆盖数据的方法，其步骤是在寄存器传送级别内提供HDL或VHDL硬件描述模型（10），提供过滤算法或滤波规则（12 ）对于在HDL或VHDL硬件描述模型（10）中发生的信号，根据所述滤波算法或滤波规则（12）从HDL或VHDL硬件描述模型（10）提取信号，以获得相关信号，执行模拟 HDL或VHDL硬件描述模型（10）的处理（18），对每个周期中的相关信号执行检查例程（20），并将相关信号存储和/或累加在数据库（22）中。此外，本发明涉及相应的系统。

6. 发明授权

US09405870B2 Generating coverage data for a switch frequency of HDL or VHDL signals 有权
标题翻译：为HDL或VHDL信号的开关频率生成覆盖数据
公开(公告)号：US09405870B2
公开(公告)日：2016-08-02
申请号：US12205476
申请日：2008-09-05
申请人： Joerg Deutschle , Lothar Felten , Ursel Hahn , Klaus Keuerleber
发明人： Joerg Deutschle , Lothar Felten , Ursel Hahn , Klaus Keuerleber
IPC分类号： G06F17/50 , G01R31/3183
CPC分类号： G06F17/5022 , G01R31/318364 , G06F17/505
摘要： The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model within a register transfer level, providing a filtering algorithm or filtering rules for signals occurring in the HDL or VHDL hardware description model, extracting signals from the HDL or VHDL hardware description model according to said filtering algorithm or filtering rules in order to get relevant signals, performing a simulation process of the HDL or VHDL hardware description model, performing a checking routine for the relevant signals in every cycle and storing and/or cumulating the relevant signals in a data base. Further the present invention relates to a corresponding system.
摘要翻译：本发明涉及一种用于产生HDL或VHDL信号的切换频率的覆盖数据的方法，其步骤是在寄存器传送级别内提供HDL或VHDL硬件描述模型，为在所述信号中发生的信号提供滤波算法或滤波规则 HDL或VHDL硬件描述模型，根据所述滤波算法或滤波规则从HDL或VHDL硬件描述模型提取信号，以获得相关信号，执行HDL或VHDL硬件描述模型的仿真过程，执行检查程序每个周期中的相关信号，并在数据库中存储和/或累积相关信号。此外，本发明涉及相应的系统。

7. 发明申请

US20060195732A1 Method and system for executing test cases for a device under verification 审中-公开
标题翻译：为验证设备执行测试用例的方法和系统
公开(公告)号：US20060195732A1
公开(公告)日：2006-08-31
申请号：US11055839
申请日：2005-02-11
申请人： Joerg Deutschle , Harald Gerst , Joerg Walter
发明人： Joerg Deutschle , Harald Gerst , Joerg Walter
IPC分类号： G01R31/28
CPC分类号： G06F11/3688
摘要： The present invention relates to a method and system for executing test cases for a device by mapping sequences of instructions and/or operation into a data flow graph, which data flow graph includes a plurality of nodes (20) and a plurality of arcs (22) connecting the nodes (20). The method comprises a step of mapping at least one instruction or operation into the corresponding node (20) of the data flow graph, a further step of mapping sequential dependencies of said instruction and/or operation into the corresponding arcs (22) between the nodes (20), and another step of mapping parallel streams of the instructions and/or operations into the corresponding arcs (22), wherein each arc (22) originates from a single node (20) and ends in a single node (20). There are randomly generated as well as deterministic sequences of instructions and/or operations mapped into the data flow graph.
摘要翻译：本发明涉及通过将指令序列和/或操作映射到数据流图中来执行设备的测试用例的方法和系统，该数据流图包括多个节点（20）和多个弧（22 ）连接节点（20）。该方法包括将至少一个指令或操作映射到数据流图的对应节点（20）的步骤，将所述指令和/或操作的顺序依赖性映射到节点之间的相应弧（22）的另一步骤（20），以及将所述指令和/或操作的并行流映射到对应的弧（22）中的另一步骤，其中每个弧（22）源于单个节点（20）并且结束在单个节点（20）中。随机生成以及映射到数据流图中的指令和/或操作的确定性序列。

8. 发明申请

US20130110490A1 Verifying Processor-Sparing Functionality in a Simulation Environment 有权
标题翻译：在模拟环境中验证处理器备用功能
公开(公告)号：US20130110490A1
公开(公告)日：2013-05-02
申请号：US13285460
申请日：2011-10-31
申请人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
发明人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F11/202 , G06F11/2242 , G06F17/5022 , G06F2217/68
摘要： A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.
摘要翻译：模拟环境验证模拟处理器内核中的处理器维护功能。仿真环境为模拟处理器核心执行第一次仿真。在仿真期间，仿真环境创建一个模拟转储文件。在稍后的时间点，仿真环境为模拟处理器核心执行第二次仿真。模拟环境节省了模拟处理器内核的状态。然后，仿真环境通过加载先前创建的仿真模型转储文件来替代模拟处理器内核的状态。然后，仿真环境将模拟处理器核心的状态设置为执行处理器备用代码，并恢复第二次仿真。

9. 发明申请

US20090172484A1 Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs 有权
标题翻译：在并行数据流图的环境下实现序列化构造的方法
公开(公告)号：US20090172484A1
公开(公告)日：2009-07-02
申请号：US12330890
申请日：2008-12-09
申请人： Joerg Deutschle , Harald Gerst , Joerg Walter
发明人： Joerg Deutschle , Harald Gerst , Joerg Walter
IPC分类号： G01R31/28
CPC分类号： G06F11/3684 , G01R31/31813 , G01R31/318371
摘要： A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated.
摘要翻译：序列化构造在多个并行数据流图的环境中实现。静态节点附加到每个活动数据流图。停顿节点在活动数据流图的执行完成之前防止令牌传递到链中的下一个数据流图。实现串行数据流图，以提供串行执行，而没有其他数据流图是活动的。序列化节点附加到串行数据流图的起始点。序列化结束节点附加到串行数据流图的端点。串行化节点被激活以开始串行操作。序列化结束节点在串行操作终止后被激活。

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