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1. 发明授权

US08987818B1 Integrated MOS power transistor with thin gate oxide and low gate charge 有权
标题翻译：具有薄栅极氧化物和低栅极电荷的集成MOS功率晶体管
公开(公告)号：US08987818B1
公开(公告)日：2015-03-24
申请号：US13312827
申请日：2011-12-06
申请人： Joel Montgomery McGregor , Vishnu Khemka
发明人： Joel Montgomery McGregor , Vishnu Khemka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/402
摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap, thereby forming a bridge having the same doping type as the substrate body. The field plate also extends over a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor.
摘要翻译：分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，形成在衬底的表面上的栅氧化层，以及形成在栅极氧化物层上的分裂多晶硅层。多晶硅层被切割成两个电隔离部分，第一部分形成位于衬底的沟道区上的多晶硅栅极，以及形成在衬底的过渡区域的一部分上的多晶硅场板的第二部分。两个多晶硅部分被间隙隔开。将轻掺杂区域注入到间隙下方的衬底中，从而形成具有与衬底本体相同的掺杂类型的桥。场板还在形成在衬底中的场氧化物填充沟槽上延伸。场板电耦合到分离栅功率晶体管的源极。

2. 发明授权

US08946851B1 Integrated MOS power transistor with thin gate oxide and low gate charge 有权
标题翻译：具有薄栅极氧化物和低栅极电荷的集成MOS功率晶体管
公开(公告)号：US08946851B1
公开(公告)日：2015-02-03
申请号：US13446987
申请日：2012-04-13
申请人： Joel Montgomery McGregor , Vishnu Khemka
发明人： Joel Montgomery McGregor , Vishnu Khemka
IPC分类号： H01L23/58
CPC分类号： H01L29/7835 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/402
摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.
摘要翻译：分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，其具有作为第一掺杂区的相反类型的第一掺杂区和第二掺杂区，形成在衬底表面上的栅氧化层，在栅极氧化物层上形成分裂的多晶硅层。将多晶硅层切割成两个电隔离部分，形成位于衬底的沟道区域和过渡区域上方的多晶硅栅极的第一部分，以及形成在形成在场氧化物填充沟槽上的整个场中的多晶硅场板的第二部分第二掺杂区域。两个多晶硅部分被间隙隔开。将轻掺杂区域注入到间隙下方的衬底中并与沟槽相邻，由此形成具有与第一掺杂区域相同的掺杂类型的填充区域。

3. 发明授权

US08963241B1 Integrated MOS power transistor with poly field plate extension for depletion assist 有权
标题翻译：集成MOS功率晶体管，具有多场扩展功能，用于耗尽辅助
公开(公告)号：US08963241B1
公开(公告)日：2015-02-24
申请号：US13460717
申请日：2012-04-30
申请人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
发明人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0653 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/402 , H01L29/4238 , H01L29/7835
摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
摘要翻译：分离栅极功率晶体管包括掺杂衬底，衬底上的栅氧化层，以及形成多晶硅栅极和多晶硅场板的栅极氧化物层上的分裂多晶硅层。两个多晶硅部分被间隙隔开。场板电耦合到分离栅功率晶体管的源极。一个或多个多晶硅延伸片从场板延伸到至少在第一掺杂区的边缘上方。多晶硅栅极被切割以形成朝向主体衬底延伸的每个多晶硅延伸片的端部的切出区域。一个或多个多晶硅延伸片将场板下面的过渡区域的部分强制为深度耗尽，从而防止在该区域中形成空穴反转层。

4. 发明申请

US20070221967A1 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US20070221967A1
公开(公告)日：2007-09-27
申请号：US11390796
申请日：2006-03-27
申请人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1083 , H01L29/7816
摘要： A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).
摘要翻译：半导体器件可以包括具有第一掺杂剂类型的半导体衬底。半导体衬底内的第一半导体区域可以具有多个第一和第二部分（44,45）。第一部分（44）可以具有第一厚度，并且第二部分（54）可以具有第二厚度。第一半导体区域可以具有第二掺杂剂类型。半导体衬底内的多个第二半导体区域（42）可以各自定位在第一半导体区域的第一部分（44）的相应一个的正下方并直接位于第一半导体区域的第一部分（44）的下方中的至少一个，并且横向地位于相应的一对第二半导体区域第一半导体区域的部分（54）。半导体衬底内的第三半导体区域（56）可以具有第一掺杂剂类型。栅电极（64）可以在第一半导体区域的至少一部分和第三半导体区域（56）的至少一部分之上。

5. 发明申请

US20070200136A1 Isolated zener diodes 审中-公开
标题翻译：隔离齐纳二极管
公开(公告)号：US20070200136A1
公开(公告)日：2007-08-30
申请号：US11364769
申请日：2006-02-28
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd Roggenbauer
IPC分类号： H01L29/00
CPC分类号： H01L29/866 , H01L29/0692
摘要： The present disclosure relates to isolated Zener diodes (100) that are substantially free of substrate current injection when forward biased. In particular, the Zener diodes (100) include an “isolation tub” structure that includes surrounding walls (150, 195) and a base (130) formed of semiconductor regions. In addition, the diodes (100) include silicide block (260) extending between anode (210) and cathode (220) regions. The reduction or elimination of substrate current injection overcomes a significant shortcoming of conventional Zener diodes that generally all suffer from substrate current injection when they are forward biased. Due to this substrate current injection, the current from each of a conventional diode's two terminals is not the same.
摘要翻译：本公开涉及在正向偏置时基本上不含衬底电流注入的隔离齐纳二极管（100）。特别地，齐纳二极管（100）包括包括由半导体区形成的周围壁（150,195）和基座（130）的“隔离桶”结构。此外，二极管（100）包括在阳极（210）和阴极（220）区域之间延伸的硅化物块（260）。衬底电流注入的减少或消除克服了常规齐纳二极管的显着缺点，当它们正向偏置时，其通常都遭受衬底电流注入。由于这种衬底电流注入，来自常规二极管的两个端子中的每一个的电流是不相同的。

6. 发明申请

US20060267089A1 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060267089A1
公开(公告)日：2006-11-30
申请号：US11142111
申请日：2005-05-31
申请人： Vishnu Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7393 , H01L29/66325
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130). In a particular embodiment, the second semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias potential applied across the semiconductor component.
摘要翻译：一种半导体元件和制造方法，包括绝缘栅双极晶体管（IGBT）（100,200），其包括具有第一导电类型的半导体衬底（110）和具有第二导电类型的掩埋半导体区域（115）半导体衬底。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120），具有位于第一半导体区域的至少一部分上方的第二导电类型的第二半导体区域（130），发射极 150），并且具有设置在第一半导体区域中的具有第二导电类型的集电极（170）。提供沉降片区域（140）以将掩埋的半导体区域（115）电连接到第二半导体区域（130）。在特定实施例中，响应于施加在半导体部件上的反向偏置电位，第二半导体区域和掩埋半导体区域耗尽第一半导体区域。

7. 发明申请

US20050242371A1 High current MOS device with avalanche protection and method of operation 审中-公开
标题翻译：大电流MOS器件具有雪崩保护和操作方法
公开(公告)号：US20050242371A1
公开(公告)日：2005-11-03
申请号：US10836730
申请日：2004-04-30
申请人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
IPC分类号： H01L27/07 , H01L29/08 , H01L29/423 , H01L29/78 , H01L31/113
CPC分类号： H01L29/0847 , H01L27/0722 , H01L29/42368 , H01L29/7835
摘要： Particularly in high current applications, impact ionization induced electron-hole pairs are generated in the drain of an MOS transistor that can cause a parasitic bipolar transistor to become destructively conductive. The holes pass through the body region of the MOS transistor, which has intrinsic resistance, to the source, which is typically held at a relatively low voltage, such as ground. The hole current causes a voltage to develop in the body region, which acts as the base. This increased base voltage is what can cause the parasitic bipolar transistor to become conductive. The likelihood of this is greatly reduced by developing a voltage between the source, which acts as the emitter, and the body region by passing the channel current through an impedance between the source and the body region. This causes the emitter voltage to increase as the base voltage is increased and thereby prevent the parasitic bipolar transistor from becoming conductive.
摘要翻译：特别是在高电流应用中，在MOS晶体管的漏极中产生电子 - 电子碰撞的碰撞对，这可使寄生双极晶体管变得具有破坏性的导电性。这些孔通过具有固有电阻的MOS晶体管的体区通向保持在较低电压（例如地）的源极。空穴电流导致在作为基底的身体区域中产生电压。这种增加的基极电压可以导致寄生双极晶体管导通。通过使通道电流通过源极和体区之间的阻抗，在作为发射极的源与体区之间形成电压，大大降低了这种可能性。这导致发射极电压随着基极电压的增加而增加，从而防止寄生双极晶体管导通。

8. 发明授权

US06930027B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US06930027B2
公开(公告)日：2005-08-16
申请号：US10369874
申请日：2003-02-18
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui , Michael C. Butner
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui , Michael C. Butner
IPC分类号： H01L21/308 , H01L21/762 , H01L21/425
CPC分类号： H01L21/3081 , H01L21/76229
摘要： A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.
摘要翻译：制造半导体部件的方法包括在半导体衬底（110）上形成第一电绝缘层（120）和第二电绝缘层（130）。该方法还包括通过第一和第二电绝缘层蚀刻第一沟槽（140）和第二沟槽（150）并进入半导体衬底，以及通过第二沟槽的底表面蚀刻第三沟槽（610）并且进入半导体衬底。第三沟槽在第一部分内部具有第一部分（920）和第二部分（930）。该方法还包括形成填充第一沟槽和第三沟槽的第一部分的第三电绝缘层（910），而不填充第三沟槽的第二部分，并且还包括在第二部分中形成插塞层（1010）的第三沟。

9. 发明授权

US06750524B2 Trench MOS RESURF super-junction devices 有权
标题翻译：沟槽MOS RESURF超连接器件
公开(公告)号：US06750524B2
公开(公告)日：2004-06-15
申请号：US10145524
申请日：2002-05-14
申请人： Vijay Parthasarthy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
发明人： Vijay Parthasarthy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2358
CPC分类号： H01L29/402 , H01L29/0634 , H01L29/0653 , H01L29/407 , H01L29/7802 , H01L29/7816 , H01L29/7835 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： A RESURF super-junction device (51) is provided which comprises a plurality of electrodes (53) disposed in a layer of a first material (61) having a first conductivity type. Each of the plurality of electrodes contains a second material (57) of a second conductivity type which is encased in a dielectric material (55).
摘要翻译：提供了RESURF超接合器件（51），其包括设置在具有第一导电类型的第一材料（61）的层中的多个电极（53）。多个电极中的每一个包含第二导电类型的第二材料（57），其被封装在电介质材料（55）中。

10. 发明授权

US09397233B2 High voltage deep trench capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US09397233B2
公开(公告)日：2016-07-19
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108 , H01L29/94 , H01L27/13 , H01L49/02 , H01L29/66
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

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