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1. 发明申请

US20130203245A1 METHODS FOR PFET FABRICATION USING APM SOLUTIONS 有权
标题翻译：使用APM解决方案的PFET制造方法
公开(公告)号：US20130203245A1
公开(公告)日：2013-08-08
申请号：US13564071
申请日：2012-08-01
申请人： Joanna WASYLUK , Stephan KRONHOLZ , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
发明人： Joanna WASYLUK , Stephan KRONHOLZ , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
IPC分类号： H01L21/20
CPC分类号： H01L21/02057 , H01L21/30604 , H01L21/30608 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
摘要翻译：一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。第一部分和第二部分由浅沟槽隔离特征电隔离。该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

2. 发明授权

US08703620B2 Methods for PFET fabrication using APM solutions 有权
标题翻译：使用APM解决方案的PFET制造方法
公开(公告)号：US08703620B2
公开(公告)日：2014-04-22
申请号：US13564071
申请日：2012-08-01
申请人： Joanna Wasyluk , Stephan Kronholz , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
发明人： Joanna Wasyluk , Stephan Kronholz , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L21/30604 , H01L21/30608 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
摘要翻译：一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。第一部分和第二部分通过浅沟槽隔离特征电隔离。该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

3. 发明申请

US20140011367A1 Low Temperature Etching of Silicon Nitride Structures Using Phosphoric Acid Solutions 失效
标题翻译：使用磷酸溶液的氮化硅结构的低温蚀刻
公开(公告)号：US20140011367A1
公开(公告)日：2014-01-09
申请号：US13541397
申请日：2012-07-03
申请人： Gregory Nowling , John Foster
发明人： Gregory Nowling , John Foster
IPC分类号： H01L21/306
CPC分类号： H01L21/31111 , H01L21/67086 , H01L29/6653
摘要： Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
摘要翻译：提供了用于处理半导体衬底的方法。该方法包括使用保持在低温（例如约110℃至130℃）之间的磷酸溶液来蚀刻氮化硅结构。这些温度提供足够的蚀刻速率，并且不会损坏周围的金属硅化物和氧化硅结构。氮化硅的蚀刻速率可以为每分钟10埃或更高。较低的温度也允许蚀刻溶液中磷酸的浓度降低，在一些实施方案中磷酸的浓度可以小于90重量％。结果，可以实现对氮化硅结构的更多的选择性蚀刻。相对于硅化物和氧化硅结构，该选择性可高达百倍。通过该蚀刻工艺，硅化物结构的表面电导率可以保持基本不变。

4. 发明授权

US08716146B2 Low temperature etching of silicon nitride structures using phosphoric acid solutions 失效
标题翻译：使用磷酸溶液对氮化硅结构进行低温蚀刻
公开(公告)号：US08716146B2
公开(公告)日：2014-05-06
申请号：US13541397
申请日：2012-07-03
申请人： Gregory Nowling , John Foster
发明人： Gregory Nowling , John Foster
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/67086 , H01L29/6653
摘要： Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
摘要翻译：提供了用于处理半导体衬底的方法。该方法包括使用保持在低温（例如约110℃至130℃）之间的磷酸溶液来蚀刻氮化硅结构。这些温度提供足够的蚀刻速率，并且不会损坏周围的金属硅化物和氧化硅结构。氮化硅的蚀刻速率可以为每分钟10埃或更高。较低的温度也允许蚀刻溶液中磷酸的浓度降低，在一些实施方案中磷酸的浓度可以小于90重量％。结果，可以实现对氮化硅结构的更多的选择性蚀刻。相对于硅化物和氧化硅结构，该选择性可高达百倍。通过该蚀刻工艺，硅化物结构的表面电导率可以保持基本不变。

5. 发明申请

US20160255824A1 Insect Trapping Device 审中-公开
标题翻译：昆虫捕获装置
公开(公告)号：US20160255824A1
公开(公告)日：2016-09-08
申请号：US14640064
申请日：2015-03-06
申请人： John Foster
发明人： John Foster
IPC分类号： A01M3/00 , A01M3/02
CPC分类号： A01M3/005 , A01M3/025
摘要： An insect trapping device traps, kills and facilitates disposal of an insect. The device includes a handle which is hollow defining a conduit extending between a first end and a second end. A fan coupled to the handle in the conduit such that the fan provides suction into the first end of the handle. A cup is coupled to the first end of the handle for directing an insect into the first end of the handle. A receptacle is coupled to the second end of the handle and vented end such that the fan urges air flow out through the receptacle wherein the receptacle receives and holds the insect sucked through the first end of the handle.
摘要翻译：昆虫捕获装置捕获，杀死并促进昆虫的处置。该装置包括一个手柄，该手柄是中空的，限定了在第一端和第二端之间延伸的导管。风扇，其联接到管道中的把手，使得风扇向手柄的第一端提供抽吸。杯子联接到手柄的第一端，以将昆虫引导到手柄的第一端。容器连接到手柄的第二端和通风端，使得风扇促使空气通过容器流出，其中容器容纳并保持通过手柄的第一端吸入的昆虫。

6. 发明授权

US08854067B2 Circular transmission line methods compatible with combinatorial processing of semiconductors 有权
标题翻译：圆形传输线方法兼容半导体的组合处理
公开(公告)号：US08854067B2
公开(公告)日：2014-10-07
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08 , G01R31/28
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

7. 发明授权

US08603837B1 High productivity combinatorial workflow for post gate etch clean development 失效
公开(公告)号：US08603837B1
公开(公告)日：2013-12-10
申请号：US13562564
申请日：2012-07-31
申请人： John Foster
发明人： John Foster
IPC分类号： H01L21/66 , H01L21/302 , H01L21/461 , C23F1/00
CPC分类号： H01L21/30604 , H01L21/02071 , H01L21/32134 , H01L21/67086 , H01L21/823828 , H01L22/12 , H01L22/20 , H01L22/30
摘要： Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

8. 发明申请

US20130316472A1 HIGH PRODUCTIVITY COMBINATORIAL OXIDE TERRACING AND PVD/ALD METAL DEPOSITION COMBINED WITH LITHOGRAPHY FOR GATE WORK FUNCTION EXTRACTION 有权
标题翻译：高生产率组合氧化物触媒和PVD / ALD金属沉积与门式工作功能提取相结合
公开(公告)号：US20130316472A1
公开(公告)日：2013-11-28
申请号：US13480023
申请日：2012-05-24
申请人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
发明人： Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
IPC分类号： H01L21/66
CPC分类号： H01L29/66181 , G01N27/002 , H01L22/14 , H01L22/20
摘要： Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
摘要翻译：使用光刻图案化的金属栅极高k电容器结构使用组合工作流程提取门功函数。氧化物梯田，以及用于金属沉积的高生产率组合工艺流程可为高性能逻辑晶体管提供最佳的高k栅介质和金属栅极解决方案。高生产率组合技术可以为PMOS和NMOS晶体管的给定高k介质金属栅极叠层提供有效的工作函数的评估，这对于识别和选择正确的材料至关重要。

9. 发明申请

US20120001033A1 EQUIPMENT MOUNTING APPARATUS AND METHOD 审中-公开
标题翻译：设备安装设备及方法
公开(公告)号：US20120001033A1
公开(公告)日：2012-01-05
申请号：US12977056
申请日：2010-12-22
申请人： Gary P. Wilde , Bryan Billingsley , Matthew Sovic , Dean Bond , John Foster , Aaron Desmond , Joshua Wilde
发明人： Gary P. Wilde , Bryan Billingsley , Matthew Sovic , Dean Bond , John Foster , Aaron Desmond , Joshua Wilde
IPC分类号： H05K7/00 , B23P11/00 , F16M13/02
CPC分类号： F16M13/02 , Y10T29/49826
摘要： An apparatus and method for mounting electronic equipment onto a pole are disclosed.
摘要翻译：公开了一种用于将电子设备安装在极上的装置和方法。

10. 发明授权

US07400096B1 Large area plasma source 失效
标题翻译：大面积等离子体源
公开(公告)号：US07400096B1
公开(公告)日：2008-07-15
申请号：US10894225
申请日：2004-07-19
申请人： John Foster , Michael Patterson
发明人： John Foster , Michael Patterson
IPC分类号： H01J7/24 , C23F1/00 , C23C14/00
CPC分类号： H01J27/18 , H01J37/32357 , H01J37/32678 , H05H1/54
摘要： An all permanent magnet Electron Cyclotron Resonance, large diameter (e.g., 40 cm) plasma source suitable for ion/plasma processing or electric propulsion, is capable of producing uniform ion current densities at its exit plane at very low power (e.g., below 200 W), and is electrodeless to avoid sputtering or contamination issues. Microwave input power is efficiently coupled with an ionizing gas without using a dielectric microwave window and without developing a throat plasma by providing a ferromagnetic cylindrical chamber wall with a conical end narrowing to an axial entrance hole for microwaves supplied on-axis from an open-ended waveguide. Permanent magnet rings are attached inside the wall with alternating polarities against the wall. An entrance magnet ring surrounding the entrance hole has a ferromagnetic pole piece that extends into the chamber from the entrance hole to a continuing second face that extends radially across an inner pole of the entrance magnet ring.
摘要翻译：适用于离子/等离子体处理或电推进的大直径（例如，40厘米）等离子体源的全永磁电子回旋加速器共振能够以非常低的功率（例如，低于200W）在其出射平面处产生均匀的离子电流密度），并且是无电极的，以避免溅射或污染问题。微波输入功率与离子化气体有效耦合，而不需要使用电介质微波窗口，而不需要通过提供一个铁磁性圆柱形腔室壁来形成喉部等离子体，该圆柱形腔室壁的锥形端部变窄到轴向入口孔，用于从开放端波导。永久磁铁环安装在墙壁内，与墙壁交替极性。围绕入口孔的入口磁环具有铁磁极片，其从入口孔延伸到腔室中，延伸到径向穿过入口磁环的内极的连续的第二面。

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