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1. 发明申请

US20090077365A1 System and method for analyzing CPU performance from a serial link front side bus 有权
标题翻译：从串行链路前端总线分析CPU性能的系统和方法
公开(公告)号：US20090077365A1
公开(公告)日：2009-03-19
申请号：US11855436
申请日：2007-09-14
申请人： Jinsaku Masuyama , Bi-Chong Wang
发明人： Jinsaku Masuyama , Bi-Chong Wang
IPC分类号： G06F15/177
CPC分类号： G06F11/3466 , G06F9/4403 , G06F11/3476 , G06F2201/865
摘要： Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD stores boot progress information passed through an I/O buffer located between the processors and the firmware that boots the processors. Downloading of the boot progress from the RAM to an external device, such as through a serial port, provides a processor trace that is analysis and debugging of the firmware by recording processor operations through the boot progress.
摘要翻译：通过在CPLD上运行的测试模块来执行多处理器信息处理系统的引导进度监视。集成在CPLD中的RAM存储通过位于处理器和引导处理器的固件之间的I / O缓冲区传递的引导进度信息。将引导进程从RAM下载到外部设备，例如通过串行端口，通过记录处理器操作通过引导进程来提供对固件进行分析和调试的处理器跟踪。

2. 发明授权

US08069344B2 System and method for analyzing CPU performance from a serial link front side bus 有权
标题翻译：从串行链路前端总线分析CPU性能的系统和方法
公开(公告)号：US08069344B2
公开(公告)日：2011-11-29
申请号：US11855436
申请日：2007-09-14
申请人： Jinsaku Masuyama , Bi-Chong Wang
发明人： Jinsaku Masuyama , Bi-Chong Wang
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F11/3466 , G06F9/4403 , G06F11/3476 , G06F2201/865
摘要： Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD stores boot progress information passed through an I/O buffer located between the processors and the firmware that boots the processors. Downloading of the boot progress from the RAM to an external device, such as through a serial port, provides a processor trace that is analysis and debugging of the firmware by recording processor operations through the boot progress.
摘要翻译：通过在CPLD上运行的测试模块来执行多处理器信息处理系统的引导进度监视。集成在CPLD中的RAM存储通过位于处理器和引导处理器的固件之间的I / O缓冲区传递的引导进度信息。将引导进程从RAM下载到外部设备，例如通过串行端口，通过记录处理器操作通过引导进程来提供对固件进行分析和调试的处理器跟踪。

3. 发明申请

US20120159238A1 System and Method for Recovering from a Configuration Error 有权
标题翻译：从配置错误中恢复的系统和方法
公开(公告)号：US20120159238A1
公开(公告)日：2012-06-21
申请号：US12970557
申请日：2010-12-16
申请人： Bi-Chong Wang
发明人： Bi-Chong Wang
IPC分类号： G06F11/14
CPC分类号： G06F11/0793 , G06F9/4406 , G06F11/0727 , G06F11/0751 , G06F11/079 , G06F11/1417 , G06F11/142 , G06F11/1425
摘要： A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.
摘要翻译：公开了一种用于从配置错误中恢复的系统和方法。基本输入输出系统（BIOS）配置与信息处理系统的节点相关联的存储器，并且在配置存储器期间启用进度监视处理。如果BIOS确定发生配置错误并修改了与存储器相关联的存储器参考代码，以防止信息处理系统的重置，则存储器被禁用。

4. 发明申请

US20100023737A1 TEST MODE INITIALIZATION 有权
标题翻译：测试模式初始化
公开(公告)号：US20100023737A1
公开(公告)日：2010-01-28
申请号：US12178887
申请日：2008-07-24
申请人： Dirie Herzi , Madhusudhan Rangarajan , Bi-Chong Wang
发明人： Dirie Herzi , Madhusudhan Rangarajan , Bi-Chong Wang
IPC分类号： G06F15/177
CPC分类号： G06F11/2284
摘要： A test mode initialization system includes beginning a power-on self-test (POST) wherein the POST may be performed by determining whether a system under test is in a quick test mode, and in response to being in the quick test mode, initialize only a portion of all memory in the system under test and initialize only a portion of a plurality of central processor unit (CPU) cores.
摘要翻译：测试模式初始化系统包括开始开机自检（POST），其中POST可以通过确定被测系统是否处于快速测试模式，并且响应于处于快速测试模式，仅初始化被测系统中的所有存储器的一部分，并且仅初始化多个中央处理器单元（CPU）核心的一部分。

5. 发明申请

US20120117302A1 System and Method for Providing Instant Video in an Information Handling System 有权
标题翻译：在信息处理系统中提供即时视频的系统和方法
公开(公告)号：US20120117302A1
公开(公告)日：2012-05-10
申请号：US12941544
申请日：2010-11-08
申请人： Bi-Chong Wang , Austin P. Bolen , Madhusudhan Rangarajan
发明人： Bi-Chong Wang , Austin P. Bolen , Madhusudhan Rangarajan
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/4401 , G06F9/4411
摘要： Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
摘要翻译：在初始化信息处理系统的存储器之前，一种方法包括将用于图形接口设备的视频选项ROM代码的图像加载到与信息处理系统的处理器相关联的高速缓存器，以及执行视频选项ROM代码以初始化图形界面设备。该方法还包括执行存储器参考代码以初始化存储器，以及在执行存储器参考代码时，从图形接口设备提供状态信息。

6. 发明授权

US08122208B2 System and method for memory architecture configuration 有权
标题翻译：内存架构配置的系统和方法
公开(公告)号：US08122208B2
公开(公告)日：2012-02-21
申请号：US12411105
申请日：2009-03-25
申请人： Bi-Chong Wang , Vijay Nijhawan , Robert Volentine
发明人： Bi-Chong Wang , Vijay Nijhawan , Robert Volentine
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0638 , G06F12/0646
摘要： Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.
摘要翻译：公开了用于减少与物理不对称的存储器结构相关联的问题和缺点的系统和方法。一种用于在具有多个存储器的信息处理系统中配置存储器的方法，每个存储器局部于多个节点中的一个，并且其中所述多个存储器中的至少一个存储器具有与至少一个其他存储器不同的存储器容量提供多个存储器。该方法可以包括确定多个存储器的最小存储容量。该方法还可以包括使用等于最小存储器容量的每个存储器的一部分来分配节点交织的存储器。对于未完全分配给节点交织的存储器的每个特定存储器，未分配给节点交织的存储器的每个特定存储器的每个部分可以与特定存储器本地的节点相关联。

7. 发明授权

US07734905B2 System and method for preventing an operating-system scheduler crash 有权
标题翻译：防止操作系统调度程序崩溃的系统和方法
公开(公告)号：US07734905B2
公开(公告)日：2010-06-08
申请号：US11405229
申请日：2006-04-17
申请人： Bi-Chong Wang , Wuxian Wu
发明人： Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F13/24 , G06F15/177
CPC分类号： G06F9/4825
摘要： System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register. A scheduler timer associated with the operating system is updated.
摘要翻译：公开了用于防止计算机系统中的操作系统调度器由于未清除的周期性中断而导致的崩溃的系统和方法。使用驻留在芯片组上的实时时钟（RTC）产生周期性中断。如果状态寄存器指示没有周期性中断已经挂起，则表示周期性中断的标志被输入到驻留在CMOS芯片上的固件中与RTC相关联的状态寄存器。与RTC相关联的中断处理程序尝试处理周期性中断，如果挂起。如果在预设的时间间隔过后周期性中断待处理，驻留在与芯片组耦合的存储器单元上的基本输入输出系统（BIOS）产生系统管理中断（SMI）。如果在预设时间间隔过后周期性中断待处理，驻留在存储器单元上的固件SMI处理器将从状态寄存器清除待处理的周期性中断。与操作系统相关联的调度器定时器被更新。

8. 发明申请

US20140304546A1 SYSTEM AND METHOD FOR RECOVERING FROM A CONFIGURATION ERROR 有权
标题翻译：从配置错误中恢复的系统和方法
公开(公告)号：US20140304546A1
公开(公告)日：2014-10-09
申请号：US14311081
申请日：2014-06-20
申请人： Bi-Chong Wang
发明人： Bi-Chong Wang
IPC分类号： G06F11/14
CPC分类号： G06F11/0793 , G06F9/4406 , G06F11/0727 , G06F11/0751 , G06F11/079 , G06F11/1417 , G06F11/142 , G06F11/1425
摘要： A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.
摘要翻译：公开了一种用于从配置错误中恢复的系统和方法。基本输入输出系统（BIOS）配置与信息处理系统的节点相关联的存储器，并且在配置存储器期间启用进度监视处理。如果BIOS确定发生配置错误并修改了与存储器相关联的存储器参考代码，以防止信息处理系统的重置，则存储器被禁用。

9. 发明申请

US20100192029A1 Systems and Methods for Logging Correctable Memory Errors 有权
标题翻译：记录可纠正内存错误的系统和方法
公开(公告)号：US20100192029A1
公开(公告)日：2010-07-29
申请号：US12361814
申请日：2009-01-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
IPC分类号： G06F11/22
CPC分类号： G06F11/2284
摘要： In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
摘要翻译：根据本公开的某些实施例，提供了一种信息处理系统。信息处理系统可以包括多个处理器，每个处理器包括多个核心，耦合到多个处理器的存储器系统以及耦合到多个处理器的控制器。控制器可以被配置为：接收关于与多个核心中的至少一个相关联的错误的本地系统管理中断（SMI）信号，确定接收到的本地SMI信号基于全局SMI触发规则触发全局SMI，导致所述多个处理器进入全局系统管理模式（SMM），并且在所述全局SMM期间将所述错误记录在由所述多个处理器共享的共享资源中。

10. 发明申请

US20080082710A1 System and method for managing system management interrupts in a multiprocessor computer system 审中-公开
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US20080082710A1
公开(公告)日：2008-04-03
申请号：US11540804
申请日：2006-09-29
申请人： Vijay Nijhawan , Madhusudhan Rangarajan , Bi-Chong Wang , Wuxian Wu
发明人： Vijay Nijhawan , Madhusudhan Rangarajan , Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： A system and method is disclosed in which, during the execution of an interrupt handling sequence in one of the processor of a multiprocessor system, a processors write a reason code to a status register to identify the cause of the interrupt. The BIOS code of the system writes to an interrupt initiation register to cause each of the processors to enter an interrupt handling sequence. Each of the processors of the system handling the interrupt on the basis of the content of the status register, resulting in each of the processors synchronously handling an interrupt for an event that would otherwise result in a local interrupt.
摘要翻译：公开了一种系统和方法，其中在多处理器系统的处理器之一执行中断处理序列期间，处理器将原因代码写入状态寄存器以识别中断的原因。系统的BIOS代码写入中断启动寄存器，使每个处理器进入中断处理程序。基于状态寄存器的内容处理中断的系统的每个处理器，导致每个处理器同步处理否则将导致本地中断的事件的中断。

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