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1. 发明申请

US20100192029A1 Systems and Methods for Logging Correctable Memory Errors 有权
标题翻译：记录可纠正内存错误的系统和方法
公开(公告)号：US20100192029A1
公开(公告)日：2010-07-29
申请号：US12361814
申请日：2009-01-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
IPC分类号： G06F11/22
CPC分类号： G06F11/2284
摘要： In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
摘要翻译：根据本公开的某些实施例，提供了一种信息处理系统。信息处理系统可以包括多个处理器，每个处理器包括多个核心，耦合到多个处理器的存储器系统以及耦合到多个处理器的控制器。控制器可以被配置为：接收关于与多个核心中的至少一个相关联的错误的本地系统管理中断（SMI）信号，确定接收到的本地SMI信号基于全局SMI触发规则触发全局SMI，导致所述多个处理器进入全局系统管理模式（SMM），并且在所述全局SMM期间将所述错误记录在由所述多个处理器共享的共享资源中。

2. 发明申请

US20080082710A1 System and method for managing system management interrupts in a multiprocessor computer system 审中-公开
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US20080082710A1
公开(公告)日：2008-04-03
申请号：US11540804
申请日：2006-09-29
申请人： Vijay Nijhawan , Madhusudhan Rangarajan , Bi-Chong Wang , Wuxian Wu
发明人： Vijay Nijhawan , Madhusudhan Rangarajan , Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： A system and method is disclosed in which, during the execution of an interrupt handling sequence in one of the processor of a multiprocessor system, a processors write a reason code to a status register to identify the cause of the interrupt. The BIOS code of the system writes to an interrupt initiation register to cause each of the processors to enter an interrupt handling sequence. Each of the processors of the system handling the interrupt on the basis of the content of the status register, resulting in each of the processors synchronously handling an interrupt for an event that would otherwise result in a local interrupt.
摘要翻译：公开了一种系统和方法，其中在多处理器系统的处理器之一执行中断处理序列期间，处理器将原因代码写入状态寄存器以识别中断的原因。系统的BIOS代码写入中断启动寄存器，使每个处理器进入中断处理程序。基于状态寄存器的内容处理中断的系统的每个处理器，导致每个处理器同步处理否则将导致本地中断的事件的中断。

3. 发明申请

US20080082711A1 System and method for managing system management interrupts in a multiprocessor computer system 有权
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US20080082711A1
公开(公告)日：2008-04-03
申请号：US11540805
申请日：2006-09-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译：公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。主处理器将识别系统管理中断的启动。主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。如果是这样，系统管理中断由本地处理器处理。在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。

4. 发明授权

US08122176B2 System and method for logging system management interrupts 有权
标题翻译：用于记录系统管理中断的系统和方法
公开(公告)号：US08122176B2
公开(公告)日：2012-02-21
申请号：US12361814
申请日：2009-01-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
IPC分类号： G06F13/24
CPC分类号： G06F11/2284
摘要： In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
摘要翻译：根据本公开的某些实施例，提供了一种信息处理系统。信息处理系统可以包括多个处理器，每个处理器包括多个核心，耦合到多个处理器的存储器系统以及耦合到多个处理器的控制器。控制器可以被配置为：接收关于与多个核心中的至少一个相关联的错误的本地系统管理中断（SMI）信号，确定接收的本地SMI信号基于全局SMI触发规则触发全局SMI，导致所述多个处理器进入全局系统管理模式（SMM），并且在所述全局SMM期间将所述错误记录在由所述多个处理器共享的共享资源中。

5. 发明授权

US07721034B2 System and method for managing system management interrupts in a multiprocessor computer system 有权
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US07721034B2
公开(公告)日：2010-05-18
申请号：US11540805
申请日：2006-09-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译：公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。主处理器将识别系统管理中断的启动。主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。如果是这样，系统管理中断由本地处理器处理。在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。

6. 发明授权

US08122208B2 System and method for memory architecture configuration 有权
标题翻译：内存架构配置的系统和方法
公开(公告)号：US08122208B2
公开(公告)日：2012-02-21
申请号：US12411105
申请日：2009-03-25
申请人： Bi-Chong Wang , Vijay Nijhawan , Robert Volentine
发明人： Bi-Chong Wang , Vijay Nijhawan , Robert Volentine
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0638 , G06F12/0646
摘要： Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.
摘要翻译：公开了用于减少与物理不对称的存储器结构相关联的问题和缺点的系统和方法。一种用于在具有多个存储器的信息处理系统中配置存储器的方法，每个存储器局部于多个节点中的一个，并且其中所述多个存储器中的至少一个存储器具有与至少一个其他存储器不同的存储器容量提供多个存储器。该方法可以包括确定多个存储器的最小存储容量。该方法还可以包括使用等于最小存储器容量的每个存储器的一部分来分配节点交织的存储器。对于未完全分配给节点交织的存储器的每个特定存储器，未分配给节点交织的存储器的每个特定存储器的每个部分可以与特定存储器本地的节点相关联。

7. 发明申请

US20100250876A1 System and Method for Memory Architecture Configuration 有权
标题翻译：内存架构配置的系统和方法
公开(公告)号：US20100250876A1
公开(公告)日：2010-09-30
申请号：US12411105
申请日：2009-03-25
申请人： Bi-Chong Wang , Vijay Nijhawan , Robert Volentine
发明人： Bi-Chong Wang , Vijay Nijhawan , Robert Volentine
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06
CPC分类号： G06F12/0607 , G06F12/0638 , G06F12/0646
摘要： Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.
摘要翻译：公开了用于减少与物理不对称的存储器结构相关联的问题和缺点的系统和方法。一种用于在具有多个存储器的信息处理系统中配置存储器的方法，每个存储器局部于多个节点之一，并且其中所述多个存储器中的至少一个存储器具有与至少一个其他存储器不同的存储器容量提供多个存储器。该方法可以包括确定多个存储器的最小存储容量。该方法还可以包括使用等于最小存储器容量的每个存储器的一部分来分配节点交织的存储器。对于未完全分配给节点交织的存储器的每个特定存储器，未分配给节点交织的存储器的每个特定存储器的每个部分可以与特定存储器本地的节点相关联。

8. 发明授权

US07620860B2 System and method of dynamically mapping out faulty memory areas 有权
标题翻译：动态映射出故障存储区域的系统和方法
公开(公告)号：US07620860B2
公开(公告)日：2009-11-17
申请号：US11851683
申请日：2007-09-07
申请人： Bi-Chong Wang , Vijay Nijhawan
发明人： Bi-Chong Wang , Vijay Nijhawan
IPC分类号： G11C29/00
CPC分类号： G11C29/72
摘要： An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory.
摘要翻译：公开了一种信息处理系统，并且可以包括处理器和耦合到处理器的存储器。此外，系统可以包括处理器可访问的系统保留区域。系统保留区域可以包括具有多个位的物理存储器故障表，物理存储器故障表中的每个位可表示存储器的相等块。

9. 发明申请

US20090070642A1 SYSTEM AND METHOD OF DYNAMICALLY MAPPING OUT FAULTY MEMORY AREAS 有权
标题翻译：动态映射失效记忆领域的系统与方法
公开(公告)号：US20090070642A1
公开(公告)日：2009-03-12
申请号：US11851683
申请日：2007-09-07
申请人： Bi-Chong Wang , Vijay Nijhawan
发明人： Bi-Chong Wang , Vijay Nijhawan
IPC分类号： G11C29/04 , G06F11/30
CPC分类号： G11C29/72
摘要： An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory.
摘要翻译：公开了一种信息处理系统，并且可以包括处理器和耦合到处理器的存储器。此外，系统可以包括处理器可访问的系统保留区域。系统保留区域可以包括具有多个位的物理存储器故障表，物理存储器故障表中的每个位可表示存储器的相等块。

10. 发明申请

US20070083728A1 System and method for enumerating multi-level processor-memory affinities for non-uniform memory access systems 有权
标题翻译：用于枚举非均匀内存访问系统的多级处理器内存亲和度的系统和方法
公开(公告)号：US20070083728A1
公开(公告)日：2007-04-12
申请号：US11247036
申请日：2005-10-11
申请人： Vijay Nijhawan , Saurabh Gupta , Bi-Chong Wang , Wuxian Wu
发明人： Vijay Nijhawan , Saurabh Gupta , Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F9/5016 , G06F2212/2542
摘要： A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.
摘要翻译：公开了一种用于枚举用于非均匀存储器访问系统的多级处理器 - 存储器亲和度的系统和方法。使用描述如何将微处理器和存储器单元布置在信息处理系统中的存储器访问速度的至少两个特性来计算处理器 - 存储器亲和层次结构，用于信息处理系统中的微处理器和存储器单元的每个可能的配对。处理系统。然后，信息处理系统在每个处理器 - 存储器亲和层级上执行算法，以在信息处理系统中获得处理器 - 存储器相关性值，并且使用处理器 - 存储器亲和度值来填充表格。信息处理系统中的操作系统可以使用该表来在信息处理系统中的微处理器之间分配存储单元。

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