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1. 发明授权

US08058123B2 Integrated circuit and method of fabrication thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08058123B2
公开(公告)日：2011-11-15
申请号：US11946843
申请日：2007-11-29
申请人： Jinping Liu , Hai Cong , Binbin Zhou , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Hai Cong , Binbin Zhou , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

2. 发明授权

US08546873B2 Integrated circuit and method of fabrication thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08546873B2
公开(公告)日：2013-10-01
申请号：US13241215
申请日：2011-09-23
申请人： Jinping Liu , Hai Cong , Binbin Zhou , Alex Kh See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Hai Cong , Binbin Zhou , Alex Kh See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/66
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

3. 发明授权

US07745320B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07745320B2
公开(公告)日：2010-06-29
申请号：US12124177
申请日：2008-05-21
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

4. 发明授权

US07960283B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07960283B2
公开(公告)日：2011-06-14
申请号：US12825325
申请日：2010-06-28
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

5. 发明授权

US07892900B2 Integrated circuit system employing sacrificial spacers 有权
标题翻译：采用牺牲间隔物的集成电路系统
公开(公告)号：US07892900B2
公开(公告)日：2011-02-22
申请号：US12098751
申请日：2008-04-07
申请人： Huang Liu , Wei Lu , Hai Cong , Alex K. H. See , Hui Peng Koh , Meisheng Zhou
发明人： Huang Liu , Wei Lu , Hai Cong , Alex K. H. See , Hui Peng Koh , Meisheng Zhou
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
摘要翻译：一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

6. 发明授权

US07247555B2 Method to control dual damascene trench etch profile and trench depth uniformity 有权
标题翻译：控制双镶嵌沟槽蚀刻轮廓和沟槽深度均匀性的方法
公开(公告)号：US07247555B2
公开(公告)日：2007-07-24
申请号：US10767292
申请日：2004-01-29
申请人： Hai Cong , Yong Kong Siew , Liang Choo Hsia
发明人： Hai Cong , Yong Kong Siew , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76808
摘要： A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
摘要翻译：一种在双镶嵌沟槽和通孔蚀刻工艺中形成沟槽开口的方法，其通过使用称为双层的双组分硬掩模层在不同的金属间电介质IMD之间，以解决双镶嵌图案化问题，例如栅栏和子层螺旋形成。通过在双镶嵌处理中的首次图案化是铜后端（BEOL）集成的主要集成方案之一。通过第一双镶嵌方案通常使用沉积在金属间电介质（IMD）膜堆叠顶部上的硬掩模层。双镶嵌沟槽蚀刻需要在蚀刻后跨晶片的均匀沟槽深度。此外，通过顶角型材需要维护良好，没有任何围栏或小面。本方法通过使用直接沉积在金属间电介质（IMD）膜堆叠的顶部上的双组分硬掩模层来解决这些问题。

7. 发明申请

US20090108257A1 CRITICAL DIMENSION FOR TRENCH AND VIAS 有权
标题翻译： TRENCH和VIAS的关键尺寸
公开(公告)号：US20090108257A1
公开(公告)日：2009-04-30
申请号：US11927658
申请日：2007-10-29
申请人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
发明人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
摘要翻译：包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。沟槽形成在IC的外围，用作保护环。

8. 发明授权

US08293545B2 Critical dimension for trench and vias 有权
标题翻译：沟槽和通孔的关键尺寸
公开(公告)号：US08293545B2
公开(公告)日：2012-10-23
申请号：US11927658
申请日：2007-10-29
申请人： Hai Cong , Yan Shan Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
发明人： Hai Cong , Yan Shan Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
IPC分类号： G01R31/26 , H01L21/66 , H01L23/58 , H01L29/10
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
摘要翻译：包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。沟槽形成在IC的外围，用作保护环。

9. 发明申请

US20090156010A1 THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING SAME 有权
标题翻译：薄膜蚀刻方法和使用相同的半导体器件制造
公开(公告)号：US20090156010A1
公开(公告)日：2009-06-18
申请号：US11959034
申请日：2007-12-18
申请人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
发明人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
IPC分类号： H01L21/302
CPC分类号： H01J37/32963 , H01J37/32935
摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.
摘要翻译：一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻移除端点检测层。端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

10. 发明授权

US08394724B2 Processing with reduced line end shortening ratio 有权
标题翻译：处理缩短了线端缩短率
公开(公告)号：US08394724B2
公开(公告)日：2013-03-12
申请号：US11843629
申请日：2007-08-22
申请人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
发明人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
IPC分类号： H01L21/312
CPC分类号： H01L21/32137 , H01L21/32139
摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
摘要翻译：用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

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