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1. 发明授权

US07525460B1 Timing loop based on analog to digital converter output and method of use 有权
标题翻译：基于模数转换器输出的定时回路和使用方法
公开(公告)号：US07525460B1
公开(公告)日：2009-04-28
申请号：US11775757
申请日：2007-07-10
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.
摘要翻译：一种用于补偿模拟输入信号（如果存在）的不对称质量并且产生定时信号的装置和过程。然后将定时信号用于模数转换。

2. 发明授权

US08957793B1 Limit equalizer output based timing loop 有权
标题翻译：限制基于均衡器输出的定时循环
公开(公告)号：US08957793B1
公开(公告)日：2015-02-17
申请号：US13608365
申请日：2012-09-10
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/48
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.
摘要翻译：本公开的方面提供了一种方法。该方法包括：基于时钟信号升压从模拟信号转换的数字信号的一部分频率分量，基于升压数字信号产生判定信号，基于升压的数字信号产生定时误差信号;以及判定信号，并对定时误差信号进行滤波，生成电压信号，控制压控振荡器产生时钟信号。

3. 发明授权

US08274413B1 Limit equalizer output based timing loop 有权
标题翻译：限制基于均衡器输出的定时循环
公开(公告)号：US08274413B1
公开(公告)日：2012-09-25
申请号：US12877779
申请日：2010-09-08
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/48
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.
摘要翻译：用于产生用于驱动模数转换器（ADC）的通道时钟信号的定时回路包括：限幅器偏置回路，被配置为产生用于来自ADC的数字输出信号的不对称补偿信号，第一加法器被配置为不对称地补偿数字输出基于来自限幅偏置环路的不对称补偿信号的限幅均衡器，被配置为限制来自加法器的非对称补偿的数字输出信号的升压幅度的限幅器，被配置为基于不对称补偿的数字输出信号产生临时判定信号的限幅器来自限幅均衡器的相位检测器被配置为基于来自极限均衡器的非对称补偿数字输出信号和来自限幅器的临时判定信号产生定时误差信号; 并且第一滤波器被配置为基于来自相位检测器的时间误差信号产生用于驱动ADC的时钟信号。

4. 发明授权

US07825836B1 Limit equalizer output based timing loop 有权
标题翻译：限制基于均衡器输出的定时循环
公开(公告)号：US07825836B1
公开(公告)日：2010-11-02
申请号：US12019430
申请日：2008-01-24
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/48
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.
摘要翻译：用于产生用于驱动模数转换器（ADC）的通道时钟信号的定时回路包括：限幅器偏置回路，被配置为产生用于来自ADC的数字输出信号的不对称补偿信号，第一加法器被配置为不对称地补偿数字输出基于来自限幅偏置环路的不对称补偿信号的限幅均衡器，被配置为限制来自加法器的非对称补偿的数字输出信号的升压幅度的限幅器，被配置为基于不对称补偿的数字输出信号产生临时判定信号的限幅器来自限幅均衡器的相位检测器被配置为基于来自极限均衡器的非对称补偿数字输出信号和来自限幅器的临时判定信号产生定时误差信号; 并且第一滤波器被配置为基于来自相位检测器的时间误差信号产生用于驱动ADC的时钟信号。

5. 发明授权

US07961124B1 Timing loop based on analog to digital converter output and method of use 有权
标题翻译：基于模数转换器输出的定时回路和使用方法
公开(公告)号：US07961124B1
公开(公告)日：2011-06-14
申请号：US12418285
申请日：2009-04-03
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/10
CPC分类号： H03M1/1255 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2537
摘要： A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.
摘要翻译：一种用于补偿模拟输入信号（如果存在）的不对称质量并且产生定时信号的装置和过程。然后将定时信号用于模数转换。

6. 发明授权

US07969848B1 System and method of decoupling asymmetry from baseline compensation 有权
标题翻译：将不对称与基线补偿分离的系统和方法
公开(公告)号：US07969848B1
公开(公告)日：2011-06-28
申请号：US12017786
申请日：2008-01-22
申请人： Jin Xie , Mats Oberg , Jingfeng Liu , Zachary Keirn
发明人： Jin Xie , Mats Oberg , Jingfeng Liu , Zachary Keirn
IPC分类号： G11B7/00
CPC分类号： G11B20/10324 , G11B7/00375 , G11B20/10009 , G11B20/10203 , G11B20/10351 , G11B2220/2537
摘要： A media defect compensation system and method may decouple effects of asymmetry from baseline error compensation computations. In some embodiments, a switching mechanism passes a baseline error signal into a baseline loop when a determination is made that a baseline error signal is not affected by asymmetry, and otherwise freezes the baseline loop when asymmetry may influence baseline error calculations.
摘要翻译：介质缺陷补偿系统和方法可以将非对称性的影响与基线误差补偿计算分离。在一些实施例中，当确定基线误差信号不受非对称性影响时，切换机构将基线误差信号传递到基线回路中，否则当不对称性可能影响基线误差计算时冻结基线回路。

7. 发明授权

US08830808B1 Method and apparatus for zero offset and gain start 有权
标题翻译：用于零偏移和增益启动的方法和装置
公开(公告)号：US08830808B1
公开(公告)日：2014-09-09
申请号：US12856762
申请日：2010-08-16
申请人： Bin Ni , Zachary Keirn , Mats Oberg
发明人： Bin Ni , Zachary Keirn , Mats Oberg
IPC分类号： G11B7/00
CPC分类号： G11B20/10009
摘要： Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes a processing path and a zero-start module. The processing path is configured to process an electrical signal that is generated in response to reading data on a storage medium. The data includes at least a first field and a second field. The electrical signal has a first profile corresponding to the first field and has a second profile corresponding to the second field. The zero-start module is configured to detect a field change from the first field to the second field, and control the processing path to add a compensation as a function of a profile change from the first profile to the second profile to keep the processed electrical signal to have a predetermined profile in response to the detected field change.
摘要翻译：本公开的方面提供了一种信号处理电路。信号处理电路包括处理路径和零起动模块。处理路径被配置为处理响应于在存储介质上读取数据而产生的电信号。该数据至少包括第一场和第二场。电信号具有对应于第一场的第一轮廓，并且具有对应于第二场的第二轮廓。零启动模块被配置为检测从第一场到第二场的场变化，并且控制处理路径以将补偿作为从第一轮廓到第二轮廓的轮廓变化的函数来添加，以保持经处理的电信号响应于检测到的场变化而具有预定的轮廓。

8. 发明申请

US20130021890A1 COLLIMATOR FOR OPTICAL PICK-UP UNITS 失效
标题翻译：光学拾取单元的聚光器
公开(公告)号：US20130021890A1
公开(公告)日：2013-01-24
申请号：US13495590
申请日：2012-06-13
申请人： Mats OBERG , Zachary Keirn
发明人： Mats OBERG , Zachary Keirn
IPC分类号： G11B7/1374 , G11B7/1376
CPC分类号： G11B7/13925 , G11B7/0945 , G11B7/1376 , G11B2007/0013
摘要： Aspects of the disclosure provide an apparatus. The apparatus includes a collimator configured to have a plurality of positions, and a controller configured to control the collimator to move to a predetermined position associated with a data layer of an optical storage medium to collimate a light beam. The collimated light beam is then focused onto the data layer of the optical storage medium.
摘要翻译：本公开的方面提供了一种装置。该装置包括被配置为具有多个位置的准直器和被配置为控制准直器移动到与光学存储介质的数据层相关联的预定位置以准直光束的控制器。然后将准直光束聚焦到光学存储介质的数据层上。

9. 发明授权

US07817512B1 Method and apparatus to correct wobble phase slip in optical recorders 有权
标题翻译：纠正光记录仪摆动相位滑移的方法和装置
公开(公告)号：US07817512B1
公开(公告)日：2010-10-19
申请号：US11925258
申请日：2007-10-26
申请人： Mats Oberg , Zachary Keirn
发明人： Mats Oberg , Zachary Keirn
IPC分类号： G11B5/09
CPC分类号： G11B7/0053 , G11B7/0941
摘要： The present disclosure can provide a method and an apparatus to correct wobble phase slip in an optical disc recording system during recording. The method of correcting a phase slip can include receiving a wobble signal of a first frequency, sampling the wobble signal to generate a sampled wobble signal, where the wobble signal is sampled at a second frequency that corresponds to a frequency of a sampling signal, comparing a phase of the sampled wobble signal with a phase of a controlled signal to generate a phase error, modifying the phase error by adding a phase bias, and adjusting the second frequency based on the modified phase error to reduce a magnitude of the modified phase error.
摘要翻译：本公开可以提供一种在记录期间校正光盘记录系统中的摆动相位滑移的方法和装置。校正相位差的方法可以包括接收第一频率的摆动信号，对摆动信号进行采样以产生采样的摆动信号，其中以对应于采样信号的频率的第二频率对摆动信号进行采样，比较具有受控信号的相位的采样摆动信号的相位以产生相位误差，通过添加相位偏差来修改相位误差，并且基于修改的相位误差来调整第二频率以减小修改的相位误差的幅度。

10. 发明授权

US08553510B1 Method and system for radial and tangential tilt calibration of optical storage systems 失效
公开(公告)号：US08553510B1
公开(公告)日：2013-10-08
申请号：US13570657
申请日：2012-08-09
申请人： Mats Oberg , Zachary Keirn , Christopher Painter
发明人： Mats Oberg , Zachary Keirn , Christopher Painter
IPC分类号： G11B7/00
CPC分类号： G11B7/0956 , G11B7/0943
摘要： A system and method for adjusting the radial tilt, tangential tilt, or a combination of radial and tangential tilt of an optical detection unit in an optical disc reading system can include applying different weighting factors to different signal components depending on which detection area detects the component, measuring a value of a signal characteristic, such as signal-to-noise ratio, of two signals with different sets of weighting factors, and determining an adjustment factor to the radial tilt as a function of the of the measured signal characteristic values.

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