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    • 1. 发明申请
    • METHOD AND APPARATUS FOR DEFECT RECOVERY
    • 缺陷恢复的方法和装置
    • WO2012071332A1
    • 2012-05-31
    • PCT/US2011/061665
    • 2011-11-21
    • MARVELL WORLD TRADE, LTD.LICONA, EstuardoMATS, Oberg
    • LICONA, EstuardoMATS, Oberg
    • G11B20/10G11B27/36
    • G11B20/10009G11B20/10027G11B20/10222G11B20/1037G11B20/10435G11B20/10481G11B27/36G11B2020/1823G11B2220/2537
    • A signal processing circuit includes a plurality of processing-circuit modules and a logic control circuit. The plurality of processing-circuit modules is configured to process an electrical signal. The plurality of processing-circuit modules has at least one processing parameter that is adaptively adjusted based on the electrical signal. The logic control circuit is configured to receive signals from the plurality of processing-circuit modules, validate the processing based on the received signals, and control a storage circuit to sample and store a value of the processing parameter when the processing is validated. Further, the logic control circuit is configured to control the storage circuit to maintain the value of processing parameter when the processing fails validation, and to control the storage circuit to recover the processing parameter in the plurality of processing-circuit modules to the stored value when the plurality of processingcircuit modules is disturbed by a defect.
    • 信号处理电路包括多个处理电路模块和逻辑控制电路。 多个处理电路模块被配置为处理电信号。 多个处理电路模块具有至少一个基于电信号自适应地调整的处理参数。 逻辑控制电路被配置为从多个处理电路模块接收信号,基于接收到的信号来验证处理,并且当处理被验证时,控制存储电路采样并存储处理参数的值。 此外,逻辑控制电路被配置为当处理失败确认时控制存储电路来维持处理参数的值,并且控制存储电路将多个处理电路模块中的处理参数恢复为存储值 多个处理电路模块受到缺陷的干扰。
    • 5. 发明授权
    • Method and apparatus for zero offset and gain start
    • 用于零偏移和增益启动的方法和装置
    • US08830808B1
    • 2014-09-09
    • US12856762
    • 2010-08-16
    • Bin NiZachary KeirnMats Oberg
    • Bin NiZachary KeirnMats Oberg
    • G11B7/00
    • G11B20/10009
    • Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes a processing path and a zero-start module. The processing path is configured to process an electrical signal that is generated in response to reading data on a storage medium. The data includes at least a first field and a second field. The electrical signal has a first profile corresponding to the first field and has a second profile corresponding to the second field. The zero-start module is configured to detect a field change from the first field to the second field, and control the processing path to add a compensation as a function of a profile change from the first profile to the second profile to keep the processed electrical signal to have a predetermined profile in response to the detected field change.
    • 本公开的方面提供了一种信号处理电路。 信号处理电路包括处理路径和零起动模块。 处理路径被配置为处理响应于在存储介质上读取数据而产生的电信号。 该数据至少包括第一场和第二场。 电信号具有对应于第一场的第一轮廓,并且具有对应于第二场的第二轮廓。 零启动模块被配置为检测从第一场到第二场的场变化,并且控制处理路径以将补偿作为从第一轮廓到第二轮廓的轮廓变化的函数来添加,以保持经处理的电 信号响应于检测到的场变化而具有预定的轮廓。
    • 10. 发明授权
    • Method and apparatus for increasing the storage capacity of an optical storage medium
    • 用于增加光学存储介质的存储容量的方法和装置
    • US08184511B1
    • 2012-05-22
    • US12953241
    • 2010-11-23
    • Mats Oberg
    • Mats Oberg
    • G11B7/00
    • G11B20/1217G11B20/10009G11B20/10037G11B20/10222G11B20/14G11B2020/1239G11B2020/1274G11B2020/1292G11B2220/2566G11B2220/257
    • A system including a demodulator module, a timing module, and a writing module. The demodulator module demodulates a wobble signal having a first period using timing signals having a second period and generates a phase error signal based on the wobble signal. The wobble signal is generated based on wobble information stored on an optical medium. The first period is a first multiple of a channel bit period of the optical medium. The second period is a second multiple of the channel bit period. The timing module generates a clock signal based on the phase error signal. The writing module writes, based on the clock signal, a predetermined number of bits on the optical medium during the first period. The predetermined number of bits written during the first period is based on the second multiple in response to the second multiple being greater than the first multiple.
    • 一种包括解调器模块,定时模块和写入模块的系统。 解调器模块使用具有第二周期的定时信号解调具有第一周期的摆动信号,并且基于摆动信号产生相位误差信号。 基于存储在光学介质上的摆动信息产生摆动信号。 第一周期是光学介质的通道位周期的第一倍数。 第二个周期是通道位周期的第二个倍数。 定时模块基于相位误差信号产生时钟信号。 写入模块在第一时段期间基于时钟信号在光学介质上写入预定数量的位。 在第一周期期间写入的预定位数是基于响应于第二倍数大于第一倍数的第二倍数。