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1. 发明授权

US07737748B2 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US07737748B2
公开(公告)日：2010-06-15
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03K3/017
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

2. 发明申请

US20080186075A1 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US20080186075A1
公开(公告)日：2008-08-07
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

3. 发明授权

US08004328B2 AC-coupling phase interpolator and delay-locked loop using the same 失效
标题翻译：交流耦合相位内插器和使用其的延迟锁定环路
公开(公告)号：US08004328B2
公开(公告)日：2011-08-23
申请号：US12570186
申请日：2009-09-30
申请人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

4. 发明申请

US20100079180A1 AC-COUPLING PHASE INTERPOLATOR AND DELAY-LOCKED LOOP USING THE SAME 失效
标题翻译：交流耦合相位插补器和延迟锁定环使用相同
公开(公告)号：US20100079180A1
公开(公告)日：2010-04-01
申请号：US12570186
申请日：2009-09-30
申请人： JIN-GOOK KIM , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： JIN-GOOK KIM , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/00 , H03H11/16
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

5. 发明申请

US20080169536A1 Semiconductor device and signal terminating method thereof 失效
标题翻译：半导体装置及其信号终端方法
公开(公告)号：US20080169536A1
公开(公告)日：2008-07-17
申请号：US12007322
申请日：2008-01-09
申请人： Dae-Hyun Chung
发明人： Dae-Hyun Chung
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L23/66 , H01L23/64 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.
摘要翻译：半导体器件可以包括半导体芯片，其包括耦合在信号输入焊盘和第一接地电压焊盘之间的信号终端电阻器，包括信号输入端子和第一接地电压端子的半导体封装件，所述信号输入端子电耦合到半导体芯片的信号输入焊盘和第一接地电压端子电耦合到半导体芯片的第一接地电压焊盘，耦合在信号输入端子和第一接地电压端子之间的电容器和电阻器，以及第一电感通过耦合信号输入端和信号输入板实现。

6. 发明授权

US07038971B2 Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof 失效
标题翻译：具有时钟接收锁定环的多时钟域数据输入处理装置及其时钟信号输入方法
公开(公告)号：US07038971B2
公开(公告)日：2006-05-02
申请号：US10288540
申请日：2002-11-06
申请人： Dae-Hyun Chung
发明人： Dae-Hyun Chung
IPC分类号： G11C8/00
CPC分类号： G06F5/06 , G11C7/1072 , G11C7/222 , H03L7/0814 , H04L7/0008 , H04L7/0037 , H04L7/0045 , H04L7/02
摘要： A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.
摘要翻译：多时钟域数据输入处理装置优选地包括：时钟信号接收同步电路，通过相位延迟第一时钟信号来产生输出时钟信号; 具有延迟锁定环（DLL）的数据输入部分; 和输入处理部。数据输入部分优选地响应于第一时钟信号输入数据，并且输入处理部分响应于具有与第一时钟信号的定时不同的定时的第二时钟信号来传送数据。用于操作多时钟域数据输入处理装置的时钟信号施加方法优选地包括以下步骤：将多个时钟信号施加到信号接收时钟转换部分; 以及将从DLL输出的延迟时钟信号应用于数据输入处理装置的其余部分。

7. 发明授权

US07863736B2 Semiconductor device and signal terminating method thereof 失效
标题翻译：半导体装置及其信号终端方法
公开(公告)号：US07863736B2
公开(公告)日：2011-01-04
申请号：US12007322
申请日：2008-01-09
申请人： Dae-Hyun Chung
发明人： Dae-Hyun Chung
IPC分类号： H01L23/50
CPC分类号： H01L23/66 , H01L23/64 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.
摘要翻译：半导体器件可以包括半导体芯片，其包括耦合在信号输入焊盘和第一接地电压焊盘之间的信号终端电阻器，包括信号输入端子和第一接地电压端子的半导体封装件，所述信号输入端子电耦合到半导体芯片的信号输入焊盘和第一接地电压端子电耦合到半导体芯片的第一接地电压焊盘，耦合在信号输入端子和第一接地电压端子之间的电容器和电阻器，以及第一电感通过耦合信号输入端和信号输入板实现。

8. 发明授权

US06812765B2 Pulsed signal transition delay adjusting circuit 失效
标题翻译：脉冲信号转换延时调整电路
公开(公告)号：US06812765B2
公开(公告)日：2004-11-02
申请号：US10425077
申请日：2003-04-28
申请人： Kyu-hyoun Kim , Dae-Hyun Chung
发明人： Kyu-hyoun Kim , Dae-Hyun Chung
IPC分类号： H03H1126
CPC分类号： H03K5/08 , H03H11/265 , H03K5/13 , H03K2005/00071
摘要： A delay circuit has an input node receives an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.
摘要翻译：延迟电路具有输入节点接收输入脉冲信号。缓冲器将输入信号传送到浮动节点。如果浮动节点处的电压低于阈值，则检测器向输出节点输出具有第一电平的输出电压，否则输出第二电平。使用两个相似的分支，一个用于控制上升转换中的延迟，一个用于控制下降转换中的延迟。对于每个分支，参考端子携带用于偏置浮动节点的参考电压。电容器和开关耦合在参考端和浮动节点之间。开关响应输出电压打开和关闭。当它打开时，它会使电容器短路。可选的相位检测器和延迟码发生器可以是反馈装置，用于连续地调节参考电压。

9. 发明授权

US06696862B2 Semiconductor memory device input circuit 有权
标题翻译：半导体存储器件输入电路
公开(公告)号：US06696862B2
公开(公告)日：2004-02-24
申请号：US10108668
申请日：2002-03-27
申请人： Dong-Jun Choi , Dae-Hyun Chung , Sang-Jun Hwang
发明人： Dong-Jun Choi , Dae-Hyun Chung , Sang-Jun Hwang
IPC分类号： H03K19096
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A semiconductor memory device input circuit including a clock selection portion. The clock selection portion receives an internal clock signal before a data strobe signal is enabled. The input circuit includes a plurality of input buffers, a clock selection circuit, a calibration circuit, and a plurality of data registers. The clock selection circuit receives a selection signal that is maintained at a first logic level for a predetermined time from the time when power is initially supplied and has a second logic level. The clock selection circuit selects a first clock signal and outputs the first clock signal as a second clock signal when the selection signal is maintained at the first logic level. The clock selection circuit selects the data strobe signal and outputs the data strobe signal as the second clock signal when the selection signal is maintained at the second logic level.
摘要翻译：一种包括时钟选择部分的半导体存储器件输入电路。时钟选择部分在数据选通信号被使能之前接收内部时钟信号。输入电路包括多个输入缓冲器，时钟选择电路，校准电路和多个数据寄存器。时钟选择电路从最初提供电源时起预定时间内接收保持在第一逻辑电平的选择信号并具有第二逻辑电平。当选择信号保持在第一逻辑电平时，时钟选择电路选择第一时钟信号并输出第一时钟信号作为第二时钟信号。当选择信号保持在第二逻辑电平时，时钟选择电路选择数据选通信号并输出数据选通信号作为第二时钟信号。

10. 发明授权

US06639868B2 SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals 失效
公开(公告)号：US06639868B2
公开(公告)日：2003-10-28
申请号：US10112108
申请日：2002-03-28
申请人： Kyu-Hyoun Kim , Dae-Hyun Chung
发明人： Kyu-Hyoun Kim , Dae-Hyun Chung
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C7/1078 , G11C2207/107
摘要： A synchronous DRAM semiconductor device including a data latch circuit outputting input data responsive to with a plurality of control signals is provided. The synchronous DRAM semiconductor device includes a first buffer for buffering an external control signal and generating a first internal control signal. A second buffer buffers the external control signal and generating a second internal control signal. A third buffer buffers the external control signal and generates an internal clock signal. A data latch circuit receives external data sequentially synchronized with the first and second internal control signals and the internal clock signal. The synchronous DRAM semiconductor device can prevent the time margin window for outputting data from the data latch circuit.

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