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1. 发明申请

US20120067636A1 INTERPOSER-EMBEDDED PRINTED CIRCUIT BOARD 有权
标题翻译：插入式嵌入式印刷电路板
公开(公告)号：US20120067636A1
公开(公告)日：2012-03-22
申请号：US13233851
申请日：2011-09-15
申请人： Jin Gu KIM , Mi Jin KIM , Young Ho KIM , Seung Wook PARK , Hee Kon LEE , Young Do KWEON
发明人： Jin Gu KIM , Mi Jin KIM , Young Ho KIM , Seung Wook PARK , Hee Kon LEE , Young Do KWEON
IPC分类号： H05K1/16 , H05K1/11
CPC分类号： H05K3/4694 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , H05K1/112 , H05K3/3436 , H05K2203/041 , H01L2224/0401
摘要： Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.
摘要翻译：本发明公开了一种嵌入式嵌入式印刷电路板，包括：基板，其具有在其一面形成并在基板的厚度方向上具有预定高度的空腔; 插入器，其设置在所述空腔中并且包括布线区域和绝缘区域; 以及形成在所述基板中并且包括与所述布线区域的一侧连接的连接图案的电路层。嵌入式嵌入式印刷电路板的优点在于，嵌入在衬底中，从而可以减小半导体封装的厚度，从而跟上半导体封装变窄的趋势。

2. 发明申请

US20120086057A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120086057A1
公开(公告)日：2012-04-12
申请号：US13252521
申请日：2011-10-04
申请人： Jin Gu KIM
发明人： Jin Gu KIM
IPC分类号： H01L29/78 , H01L21/425
CPC分类号： H01L27/11521
摘要： A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors.
摘要翻译：半导体存储器件包括形成在半导体衬底上的栅极绝缘层; 用于形成在所述栅极绝缘层上的选择晶体管和存储单元的第一导电层图案; 形成在所述第一导电层图案上的电介质层; 形成在用于存储单元的第一导电层图案上的电介质层上的第二导电层图案; 并且选择由具有比第二导电层图案低的电阻的材料制成的线并且耦合到用于选择晶体管的第一导电层图案。

3. 发明申请

US20110309524A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的形成和半导体器件金属线的方法
公开(公告)号：US20110309524A1
公开(公告)日：2011-12-22
申请号：US13222501
申请日：2011-08-31
申请人： Jin Gu KIM
发明人： Jin Gu KIM
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76802 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.
摘要翻译：形成半导体器件的金属线的半导体器件和方法包括形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的蚀刻停止层，通过蚀刻蚀刻停止层和第一绝缘层形成的接触孔绝缘层，形成在接触孔内的接触塞和形成在接触塞和蚀刻停止层之上的第二绝缘层。蚀刻第二绝缘层以形成沟槽，接触插头通过该沟槽暴露。金属线形成在沟槽内。因此，由于金属线之间不会残留具有高介电常数的硬掩模，所以可以减少金属线的电容。

4. 发明申请

US20110207287A1 METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110207287A1
公开(公告)日：2011-08-25
申请号：US12954321
申请日：2010-11-24
申请人： Myung Shik LEE , Jin Gu KIM
发明人： Myung Shik LEE , Jin Gu KIM
IPC分类号： H01L21/762
CPC分类号： H01L27/11521
摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，在隧道绝缘层上形成包括第一浓度的第一杂质离子的电荷捕获层，形成补偿层，包括第二杂质离子第二浓度，在电荷陷阱层上方，将补偿层内的第二杂质离子扩散到电荷陷阱层，去除补偿层，在电荷陷阱层的表面上形成电介质层，以及形成用于控制的导电层电介质层上的栅极。

5. 发明申请

US20080217789A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的形成和半导体器件金属线的方法
公开(公告)号：US20080217789A1
公开(公告)日：2008-09-11
申请号：US11965827
申请日：2007-12-28
申请人： Jin Gu KIM
发明人： Jin Gu KIM
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76802 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.
摘要翻译：形成半导体器件的金属线的半导体器件和方法包括形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的蚀刻停止层，通过蚀刻蚀刻停止层和第一绝缘层形成的接触孔绝缘层，形成在接触孔内的接触塞和形成在接触塞和蚀刻停止层之上的第二绝缘层。蚀刻第二绝缘层以形成沟槽，接触插头通过该沟槽暴露。金属线形成在沟槽内。因此，由于金属线之间不会残留具有高介电常数的硬掩模，所以可以减少金属线的电容。

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