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1. 发明授权

US08466473B2 Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs 有权
标题翻译：具有高k /金属栅极MOSFET的Vt调谐和短沟道控制的结构和方法
公开(公告)号：US08466473B2
公开(公告)日：2013-06-18
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L31/0312 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

2. 发明申请

US20120138953A1 STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs 有权
标题翻译：具有高K /金属栅极MOSFET的调谐和短路控制的结构和方法
公开(公告)号：US20120138953A1
公开(公告)日：2012-06-07
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

3. 发明申请

US20080023752A1 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT 审中-公开
标题翻译： BORON DOPED SiGe HALO用于NFET控制短路通道效应
公开(公告)号：US20080023752A1
公开(公告)日：2008-01-31
申请号：US11460766
申请日：2006-07-28
申请人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
发明人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.
摘要翻译：公开了一种n型场效应晶体管（NFET）和用于形成用于NFET的光晕以控制短沟道效应的方法。一种方法包括在硅衬底上形成栅极; 凹陷与栅极相邻的硅; 通过在凹槽中外延生长硼原位掺杂硅锗（SiGe）来形成卤素; 并在硅锗上外延生长硅。或者，可以通过将硼离子注入到硅衬底内的嵌入的SiGe区域中来形成卤素。所得NFET包括嵌入在硅衬底内的硼掺杂SiGe光晕。嵌入的SiGe层可以是松弛层，而不会在通道中插入应变。硼在SiGe中的高固体溶解度和低扩散速率允许形成将保持尖锐轮廓的光晕，这提供了对短通道效应的更好控制并增加了对NFET阈值电压滚降的控制。

4. 发明申请

US20110175170A1 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET 失效
标题翻译：用于制造低漏电和低失真的NMOSFET的结构和方法
公开(公告)号：US20110175170A1
公开(公告)日：2011-07-21
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

5. 发明授权

US08697521B2 Structure and method for making low leakage and low mismatch NMOSFET 失效
标题翻译：低泄漏和低失配NMOSFET的结构和方法
公开(公告)号：US08697521B2
公开(公告)日：2014-04-15
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

6. 发明授权

US08120058B2 High-drive current MOSFET 有权
标题翻译：高驱动电流MOSFET
公开(公告)号：US08120058B2
公开(公告)日：2012-02-21
申请号：US12607116
申请日：2009-10-28
申请人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
发明人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
IPC分类号： H01L29/739
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件的方法。在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

7. 发明申请

US20110095333A1 HIGH-DRIVE CURRENT MOSFET 有权
标题翻译：高驱动电流MOSFET
公开(公告)号：US20110095333A1
公开(公告)日：2011-04-28
申请号：US12607116
申请日：2009-10-28
申请人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
发明人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件的方法。在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

8. 发明授权

US09082751B2 Half-FinFET semiconductor device and related method 有权
标题翻译：半鳍FET半导体器件及相关方法
公开(公告)号：US09082751B2
公开(公告)日：2015-07-14
申请号：US13232737
申请日：2011-09-14
申请人： Xiangdong Chen , Wei Xia
发明人： Xiangdong Chen , Wei Xia
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L29/06
CPC分类号： H01L29/4236 , H01L29/0653 , H01L29/0692 , H01L29/66659 , H01L29/66787 , H01L29/7835 , H01L29/785
摘要： According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.
摘要翻译：根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域，从而导致半FinFET结构具有降低的导通电阻。

9. 发明授权

US09041171B2 Programmable interposer with conductive particles 有权
标题翻译：可编程插入式导电颗粒
公开(公告)号：US09041171B2
公开(公告)日：2015-05-26
申请号：US13340430
申请日：2011-12-29
申请人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： H01L21/326 , H01L23/495 , H05K1/11 , B82Y99/00 , H01L23/498 , H05K1/02 , H01L21/48 , H05K3/40
CPC分类号： H01L23/49827 , B82Y10/00 , H01L21/485 , H01L21/486 , H01L23/49822 , H01L2224/16225 , H05K1/029 , H05K3/4038 , H05K2201/0248 , H05K2201/026 , H05K2201/0323 , H05K2201/10378 , H05K2203/104 , H05K2203/105
摘要： An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.
摘要翻译：本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。导电颗粒可具有导电外表面。此外，导电粒子可以是球形的。导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

10. 发明授权

US08659081B2 Transistor with reduced channel length variation 有权
标题翻译：具有减小通道长度变化的晶体管
公开(公告)号：US08659081B2
公开(公告)日：2014-02-25
申请号：US13613864
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

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