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1. 发明申请

US20110149650A1 Data Transfer Flows for On-Chip Folding 有权
标题翻译：片上折叠数据传输流程
公开(公告)号：US20110149650A1
公开(公告)日：2011-06-23
申请号：US12642649
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchison , Sergey Anatolievich Gorobets
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchison , Sergey Anatolievich Gorobets
IPC分类号： G11C16/04 , G11C14/00
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C7/1042 , G11C16/10 , G11C2211/5641 , G11C2211/5643
摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分，状态格式。当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写入寄存器，并且将数据从读/写寄存器执行到多状态编程操作到非易失性存储器的第二部分的位置。多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

2. 发明授权

US08144512B2 Data transfer flows for on-chip folding 有权
标题翻译：数据传输流程用于片上折叠
公开(公告)号：US08144512B2
公开(公告)日：2012-03-27
申请号：US12642649
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchinson , Sergey Anatolievich Gorobets
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Neil David Hutchinson , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C7/1042 , G11C16/10 , G11C2211/5641 , G11C2211/5643
摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the portions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分，状态格式。当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写寄存器，并且将数据的部分的数据从读/写寄存器执行到非易失性存储器的第二部分的位置的多状态编程操作。多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

3. 发明申请

US20110153913A1 Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data 有权
标题翻译：使用片上数据折叠的多档位控制的非易失性存储器
公开(公告)号：US20110153913A1
公开(公告)日：2011-06-23
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

4. 发明授权

US08468294B2 Non-volatile memory with multi-gear control using on-chip folding of data 有权
标题翻译：具有多档位控制的非易失性存储使用片上数据折叠
公开(公告)号：US08468294B2
公开(公告)日：2013-06-18
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F3/06 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

5. 发明申请

US20080091901A1 Method for non-volatile memory with worst-case control data management 审中-公开
标题翻译：用于具有最坏情况控制数据管理的非易失性存储器的方法
公开(公告)号：US20080091901A1
公开(公告)日：2008-04-17
申请号：US11549035
申请日：2006-10-12
申请人： Alan David Bennett , Neil David Hutchison , Sergey Anatolievich Gorobets
发明人： Alan David Bennett , Neil David Hutchison , Sergey Anatolievich Gorobets
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7205
摘要： In a nonvolatile memory with a block management system, data written to blocks include host write data and also system control data for managing the blocks. When a block is full or no longer accepting data, it is closed after valid versions of the data on it are relocated to another block in a rewrite operation. An improved pre-emptive rewrite scheme prevents a worst-case situation where multiple rewrites to occur at once when they happened to be full at the same time. Particularly, the scheduling of the pre-emptive rewrites for control data is based on a number of considerations including the time required for each control block rewrite and the time available for control block rewrites based on the configuration of the update blocks for storing host data, the time required in the foreground host operation and the host write latency.
摘要翻译：在具有块管理系统的非易失性存储器中，写入块的数据包括主机写入数据以及用于管理块的系统控制数据。当块已满或不再接受数据时，在重写操作中将其上的数据的有效版本重定位到另一个块之后，它将被关闭。改进的优先重写方案可以防止在同时发生多次重写时立即发生多次重写的最坏情况。特别地，用于控制数据的优先重写的调度基于多个考虑因素，包括基于用于存储主机数据的更新块的配置，每个控制块重写所需的时间和可用于控制块重写的时间，前台主机操作所需的时间和主机写入延迟。

6. 发明申请

US20080091871A1 Non-volatile memory with worst-case control data management 审中-公开
标题翻译：具有最坏情况控制数据管理的非易失性存储器
公开(公告)号：US20080091871A1
公开(公告)日：2008-04-17
申请号：US11549040
申请日：2006-10-12
申请人： Alan David Bennett , Neil David Hutchison , Sergey Anatolievich Gorobets
发明人： Alan David Bennett , Neil David Hutchison , Sergey Anatolievich Gorobets
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7205
摘要： In a nonvolatile memory with a block management system, data written to blocks include host write data and also system control data for managing the blocks. When a block is full or no longer accepting data, it is closed after valid versions of the data on it are relocated to another block in a rewrite operation. An improved pre-emptive rewrite scheme prevents a worst-case situation where multiple rewrites to occur at once when they happened to be full at the same time. Particularly, the scheduling of the pre-emptive rewrites for control data is based on a number of considerations including the time required for each control block rewrite and the time available for control block rewrites based on the configuration of the update blocks for storing host data, the time required in the foreground host operation and the host write latency.
摘要翻译：在具有块管理系统的非易失性存储器中，写入块的数据包括主机写入数据以及用于管理块的系统控制数据。当块已满或不再接受数据时，在重写操作中将其上的数据的有效版本重定位到另一个块之后，它将被关闭。改进的优先重写方案可以防止在同时发生多次重写时立即发生多次重写的最坏情况。特别地，用于控制数据的优先重写的调度基于多个考虑因素，包括基于用于存储主机数据的更新块的配置，每个控制块重写所需的时间和可用于控制块重写的时间，前台主机操作所需的时间和主机写入延迟。

7. 发明授权

US09141528B2 Tracking and handling of super-hot data in non-volatile memory systems 有权
标题翻译：在非易失性存储器系统中跟踪和处理超热数据
公开(公告)号：US09141528B2
公开(公告)日：2015-09-22
申请号：US13556035
申请日：2012-07-23
申请人： Sergey Anatolievich Gorobets , Liam Michael Parker , Neil David Hutchison , Robert George Young , Alan David Bennett
发明人： Sergey Anatolievich Gorobets , Liam Michael Parker , Neil David Hutchison , Robert George Young , Alan David Bennett
IPC分类号： G06F12/02 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F3/068 , G06F2212/7202 , G06F2212/7211
摘要： A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. Among the units more likely to suffer subsequent rewrites, a smaller subset of data super-hot is determined. These super-hot data are then maintained in a dedicated portion of the memory, such as a resident binary zone in a memory system with both binary and MLC portions.
摘要翻译：组织成闪存可擦除块的非易失性存储器根据分配给每个数据单元的温度对数据单元进行排序，其中较高的温度指示由于垃圾收集操作而导致的数据单元将遭受后续重写的更高概率。数据单元来自主机写入或来自重定位操作。在更可能遭受后续重写的单位中，确定了数据超热的较小子集。然后，这些超热数据被保存在存储器的专用部分中，例如具有二进制和MLC部分的存储器系统中的常驻二进制区。

8. 发明申请

US20130024609A1 Tracking and Handling of Super-Hot Data in Non-Volatile Memory Systems 有权
标题翻译：在非易失性存储器系统中追踪和处理超热数据
公开(公告)号：US20130024609A1
公开(公告)日：2013-01-24
申请号：US13556035
申请日：2012-07-23
申请人： Sergey Anatolievich Gorobets , Liam Michael Parker , Neil David Hutchison , Robert George Young , Alan David Bennett
发明人： Sergey Anatolievich Gorobets , Liam Michael Parker , Neil David Hutchison , Robert George Young , Alan David Bennett
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F3/068 , G06F2212/7202 , G06F2212/7211
摘要： A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. Among the units more likely to suffer subsequent rewrites, a smaller subset of data super-hot is determined. These super-hot data are then maintained in a dedicated portion of the memory, such as a resident binary zone in a memory system with both binary and MLC portions.
摘要翻译：组织成闪存可擦除块的非易失性存储器根据分配给每个数据单元的温度对数据单元进行排序，其中较高的温度指示由于垃圾收集操作而导致的数据单元将遭受后续重写的更高概率。数据单元来自主机写入或来自重定位操作。在更可能遭受后续重写的单位中，确定了数据超热的较小子集。然后，这些超热数据被保存在存储器的专用部分中，例如具有二进制和MLC部分的存储器系统中的常驻二进制区。

9. 发明授权

US08634239B2 Hybrid multi-level cell programming sequences 有权
标题翻译：混合多级单元编程序列
公开(公告)号：US08634239B2
公开(公告)日：2014-01-21
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

10. 发明申请

US20130170293A1 HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES 有权
标题翻译：混合多级细胞编程序列
公开(公告)号：US20130170293A1
公开(公告)日：2013-07-04
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

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