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1. 发明授权

US5598369A Flash EEPROM array with floating substrate erase operation 失效
标题翻译：闪存EEPROM阵列具有浮动衬底擦除操作
公开(公告)号：US5598369A
公开(公告)日：1997-01-28
申请号：US484252
申请日：1995-06-07
申请人： Jian Chen , Nader Radjy
发明人： Jian Chen , Nader Radjy
IPC分类号： G11C17/00 , G11C16/04 , G11C16/14 , H01L27/115
CPC分类号： G11C16/14 , H01L27/115
摘要： A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue of yield sensitivity to defects in the channel, since during the erasure operation, electrons trapped in the floating gate pass through the overlap region between the source region and the control gate, instead of through the channel.
摘要翻译：通过向单元的源极区域施加相对高的正电压，并且使单元的漏极区域和衬底区域的电压浮动，从而将电池的接地电位施加到电池的控制栅极，擦除快闪EEPROM单元阵列。通过浮置衬底，由于唯一的直流电流路径在控制栅极和源极区域之间，擦除期间的源电流大大降低。由于源极电流很小，所以不需要双扩散结，使得电池可以占用给定设计规则的最小面积，并且简化了电池制造工艺。此外，抑制了高能量孔的产生，并且可以获得改善的性能。由于在擦除操作期间源极电流较小，源极区域的高正电压可以通过片上电荷泵从低至+3V的电源电压产生。这简化了许多闪存的存储器板的设计 EEPROM芯片将被放置。此外，由于在擦除期间将相对较高的正电压施加到源极区域，所以存储单元的后擦除Vt分布被紧固。最后，由于在擦除操作期间，捕获在浮置栅极中的电子通过源极区域和控制栅极之间的重叠区域而不是通过沟道，所以对通道中的缺陷的产量灵敏度没有任何问题。

2. 发明授权

US5561620A Flash EEPROM array with floating substrate erase operation 失效
标题翻译：闪存EEPROM阵列具有浮动衬底擦除操作
公开(公告)号：US5561620A
公开(公告)日：1996-10-01
申请号：US508425
申请日：1995-07-31
申请人： Jian Chen , Nader Radjy
发明人： Jian Chen , Nader Radjy
IPC分类号： G11C17/00 , G11C16/04 , G11C16/14 , H01L27/115 , G11C7/00
CPC分类号： G11C16/14 , H01L27/115
摘要： A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue of yield sensitivity to defects in the channel, since during the erasure operation, electrons trapped in the floating gate pass through the overlap region between the source region and the control gate, instead of through the channel.
摘要翻译：通过向单元的源极区域施加相对高的正电压，并且使单元的漏极区域和衬底区域的电压浮动，从而将电池的接地电位施加到电池的控制栅极，擦除快闪EEPROM单元阵列。通过浮置衬底，由于唯一的直流电流路径在控制栅极和源极区域之间，擦除期间的源电流大大降低。由于源极电流很小，所以不需要双扩散结，使得电池可以占用给定设计规则的最小面积，并且简化了电池制造工艺。此外，抑制了高能量孔的产生，并且可以获得改善的性能。由于在擦除操作期间源极电流较小，源极区域的高正电压可以通过片上电荷泵从低至+3V的电源电压产生。这简化了许多闪存的存储器板的设计 EEPROM芯片将被放置。此外，由于在擦除期间将相对较高的正电压施加到源极区域，所以存储单元的后擦除Vt分布被紧固。最后，由于在擦除操作期间，捕获在浮置栅极中的电子通过源极区域和控制栅极之间的重叠区域而不是通过沟道，所以对通道中的缺陷的产量灵敏度没有任何问题。

3. 发明授权

US5576991A Multistepped threshold convergence for a flash memory array 失效
标题翻译：闪存阵列的多级阈值收敛
公开(公告)号：US5576991A
公开(公告)日：1996-11-19
申请号：US269540
申请日：1994-07-01
申请人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
发明人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , G11C16/34 , G11C11/40
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404
摘要： A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.
摘要翻译：一种在存储器单元被擦除之后在闪存EEPROM阵列中会聚存储器单元的阈值电压的方法，该方法包括在施加漏极干扰期间施加具有初始负值的栅极电压，其逐步增加到更多的正值电压。通过施加具有初始负值的栅极电压，减小了会聚期间的漏电流，使得阵列的位线上的所有单元能够并行收敛。

4. 发明授权

US5579261A Reduced column leakage during programming for a flash memory array 失效
标题翻译：在闪存阵列编程期间降低色谱柱泄漏
公开(公告)号：US5579261A
公开(公告)日：1996-11-26
申请号：US426716
申请日：1995-04-21
申请人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
发明人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
IPC分类号： G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3409 , G11C16/26 , G11C16/3404
摘要： A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.
摘要翻译：一种用于使用热电子注入来连接到位线的闪存单元的阵列中的单元的编程方法。在该方法中，将负字线电压施加到连接到位线的未选择的单元，以在未选择的单元中产生负栅极至源极电压。提供未选择的单元中的负栅极到源极电压以防止过电压的单元或具有负阈值的单元导通以减少位线泄漏电流。

5. 发明授权

US5521867A Adjustable threshold voltage conversion circuit 失效
标题翻译：可调阈值电压转换电路
公开(公告)号：US5521867A
公开(公告)日：1996-05-28
申请号：US160057
申请日：1993-12-01
申请人： Jian Chen , Lee E. Cleveland , Shane Hollmer , Ming-Sang Kwan , David Liu , Nader Radjy
发明人： Jian Chen , Lee E. Cleveland , Shane Hollmer , Ming-Sang Kwan , David Liu , Nader Radjy
IPC分类号： G11C17/00 , G11C16/04 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404
摘要： A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.
摘要翻译：用于提供紧密擦除阈值电压分布的闪速EPROM电路。该电路包括具有门，源和漏极的存储器单元的阵列。位线耦合到存储器阵列中的一列单元的漏极。多个字线各自耦合到存储器阵列中的一行单元格的栅极。第一电压源耦合到位线以会聚被擦除的存储器单元的阈值电压。第二电压源耦合到字线以控制擦除的存储器单元的阈值电压。

6. 外观设计

USD1008676S1 Step-stool 有权
公开(公告)号：USD1008676S1
公开(公告)日：2023-12-26
申请号：US29820654
申请日：2021-12-23
申请人： Jian Chen
设计人： Jian Chen
摘要： FIG. 1 is a perspective view of a step-stool showing my new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof;
FIG. 8 is a bottom side perspective view thereof; and,
FIG. 9 is a perspective view of the step-stool of FIG. 1, shown with unclaimed patterned ornamentation.
The broken lines in the drawings depict portions of the step-stool that form no part of the claimed design.

7. 发明申请

US20200032191A1 Shock Tube and Cell Electroporation Device with the Shock Tube 审中-公开
公开(公告)号：US20200032191A1
公开(公告)日：2020-01-30
申请号：US16586989
申请日：2019-09-29
申请人： Jian Chen
发明人： Jian Chen
IPC分类号： C12M1/42 , C12M1/12 , B01L3/00
摘要： The shock tube comprises a tube, a first electrode, a second electrode and a stopple, wherein the tube is internally provided with a cavity for accommodating a target liquid sample. The first electrode is arranged at one end of the tube. The second electrode is arranged in the stopple, and the outer end of the second electrode can be electrically connected with the exterior via an opening of the stopple. The stopple is internally provided with an elastic piece connected with the second electrode. The outer side of the elastic piece is connected with the stopple, and the inner side of the elastic piece is connected with the second electrode. The invention further provides a cell electroporation device where the shock tube can be placed.

8. 发明授权

US10392634B2 Method for high-efficiency production of pinoresinol using an H2O2 auto-scavenging cascade 有权
公开(公告)号：US10392634B2
公开(公告)日：2019-08-27
申请号：US15472003
申请日：2017-03-28
申请人： Jingwen Zhou , Jian Chen , Yongkun Lv , Guocheng Du
发明人： Jingwen Zhou , Jian Chen , Yongkun Lv , Guocheng Du
IPC分类号： C12P7/22 , C12N9/04 , C12N9/08 , C12N1/20 , C12N15/00 , C07H21/04 , C12N15/62 , C12P17/18
摘要： The present invention provides a method for high-efficiency production of pinoresinol by use of an H2O2 auto-scavenging enzymatic cascade. It uses eugenol as the substrate, which is relatively inexpensive and is industrially available. It uses an enzymatic cascade to remove H2O2 produced in the process of pinoresinol synthesis, thereby reducing its inhibitory effect on the enzyme activity. In addition, the present invention uses whole cells as a catalyst, which can continuously regenerate cofactors needed by the enzyme, thus eliminating the need for exogenous addition of expensive cofactors during the reaction. The yield of the present invention can reach 7.12 g/L and the conversion rate is 61.55%.

9. 发明授权

US10085470B2 Method for improving the quality of soy sauce using Bacillus amyloliquefaciens 有权
公开(公告)号：US10085470B2
公开(公告)日：2018-10-02
申请号：US15204991
申请日：2016-07-07
申请人： Fang Fang , Jiran Zhang , Xifei Yang , Chuanwang Hu , Jian Chen , Guocheng Du
发明人： Fang Fang , Jiran Zhang , Xifei Yang , Chuanwang Hu , Jian Chen , Guocheng Du
IPC分类号： A23L5/20 , A23L27/50 , A23L23/00 , C12N1/20 , C12R1/07
摘要： The present invention provides a method for improving the quality of soy sauce using Bacillus amyloliquefaciens, which relates to the field of microbiology and food technology. The method comprises inoculating Bacillus amyloliquefaciens BBE JY06 during soy sauce fermentation. With Bacillus amyloliquefaciens addition during soy sauce fermentation, the aroma and tastes of soy sauce is improved and the ethyl carbamate content in soy sauce is decreased as well.

10. 发明授权

US09690855B2 Method and system for searching for a web document 有权
公开(公告)号：US09690855B2
公开(公告)日：2017-06-27
申请号：US13549416
申请日：2012-07-14
申请人： Sheng Hua Bao , Jian Chen , Zhong Su , Rui Wang
发明人： Sheng Hua Bao , Jian Chen , Zhong Su , Rui Wang
IPC分类号： G06F17/30
CPC分类号： G06F17/30864
摘要： Provided is a method applied to a system including a plurality of sensors, a proxy, and a server. The method includes: measuring objects by the plurality of sensors to obtain first measurement values; computing a correlation among the first measurement values by the server based on the first measurement values; computing an actual measurement value of a second measurement value by the proxy based on the first measurement values and a given function; verifying the plurality of sensors by setting one or more sensors as verification target sensors in turn by the server at predetermined timing; computing a predicted value of the second measurement value by the server based on the correlation and the first measurement values obtained from the other sensors; and outputting the predicted value of the second measurement value instead of the actual measurement value thereof at least during the verification of the verification target sensors.

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