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1. 发明授权

US4482996A Five port module as a node in an asynchronous speed independent network of concurrent processors 失效
标题翻译：五端口模块作为节点在异步速度独立的并发处理器网络中
公开(公告)号：US4482996A
公开(公告)日：1984-11-13
申请号：US414071
申请日：1982-09-02
申请人： Jesse R. Wilson , Gary L. Logsdon
发明人： Jesse R. Wilson , Gary L. Logsdon
IPC分类号： G06F15/177 , G06F15/173 , G06F15/80 , H04J6/00
CPC分类号： G06F15/17375 , G06F15/80
摘要： A five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.
摘要翻译：作为并行处理器的异步速度独立网络中的节点的五端口模块，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道，用于每个输出仲裁器交换机（与其自己的端口相关联的仲裁器交换机除外）。每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。

2. 发明授权

US4475188A Four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors 失效
标题翻译：四路仲裁器交换机，用于将五端口模块作为异步速度独立并发处理器网络中的一个节点
公开(公告)号：US4475188A
公开(公告)日：1984-10-02
申请号：US414069
申请日：1982-09-02
申请人： Jesse R. Wilson , Gary L. Logsdon
发明人： Jesse R. Wilson , Gary L. Logsdon
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , H04J6/00
CPC分类号： G06F15/17375 , G06F15/80
摘要： A four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.
摘要翻译：一种用于五端口模块作为并行处理器的异步速度独立网络中的节点的四路仲裁器交换机，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道对于每个输出仲裁器开关（除了与其自己的端口相关联的仲裁器开关外）。每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。

3. 发明授权

US4498133A Selector switch for a concurrent network of processors 失效
标题翻译：并发处理器网络的选择器开关
公开(公告)号：US4498133A
公开(公告)日：1985-02-05
申请号：US329423
申请日：1981-12-10
申请人： Brent C. Bolton , Gary L. Logsdon , Carl F. Hagenmaier, Jr. , Jesse R. Wilson
发明人： Brent C. Bolton , Gary L. Logsdon , Carl F. Hagenmaier, Jr. , Jesse R. Wilson
IPC分类号： G06F15/16 , G06F13/14 , G06F13/40 , G06F15/173 , G06F15/80 , G06F9/00
CPC分类号： G06F13/14 , G06F13/4022 , G06F15/80
摘要： Disclosed is a selector switch for use in forming an asynchronous network of concurrent processors where the selector switch receives a message from one input port and transmits it to one of two output ports. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.
摘要翻译：公开了一种用于形成并行处理器的异步网络的选择器开关，其中选择器开关从一个输入端口接收消息并将其发送到两个输出端口之一。如果由于网络中的一个节点或交换机中的组件的故障而使特定路径变得被锁定，则可以清除已经建立的通过网络的路径。

4. 发明授权

US4484325A Four way selector switch for a five port module as a node asynchronous speed independent network of concurrent processors 失效
标题翻译：四路选择开关为五端口模块作为节点异步速度独立的并发处理器网络
公开(公告)号：US4484325A
公开(公告)日：1984-11-20
申请号：US414070
申请日：1982-09-02
申请人： Jesse R. Wilson , Gary L. Logsdon
发明人： Jesse R. Wilson , Gary L. Logsdon
IPC分类号： G06F15/16 , G06F13/14 , G06F13/40 , G06F15/173 , G06F15/80 , H04J6/00
CPC分类号： G06F13/4022 , G06F13/14 , G06F15/80
摘要： A four way selector switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.
摘要翻译：一种用于五端口模块作为并行处理器的异步速度独立网络中的节点的四路选择器开关，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道对于每个输出仲裁器开关（除了与其自己的端口相关联的仲裁器开关外）。每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。

5. 发明授权

US4488151A Arbiter switch for a concurrent network of processors 失效
标题翻译：仲裁器交换机用于并发网络的处理器
公开(公告)号：US4488151A
公开(公告)日：1984-12-11
申请号：US329424
申请日：1981-12-10
申请人： Brent C. Bolton , Gary L. Logsdon , Carl F. Hagenmaier, Jr. , Jesse R. Wilson
发明人： Brent C. Bolton , Gary L. Logsdon , Carl F. Hagenmaier, Jr. , Jesse R. Wilson
IPC分类号： B61B12/10 , B61B12/00 , B66D1/50 , G06F13/14 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80 , H04Q9/00 , H04J3/02
CPC分类号： G06F15/17375 , B61B12/00 , B61B12/007 , G06F13/14 , G06F13/4022 , G06F15/80
摘要： Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.
摘要翻译：公开了一种用于形成并发处理器的异步网络的仲裁器交换机，其中仲裁器交换机从两个输入端口之一接收消息并将其发送到其输出端口。如果由于网络中的一个节点或交换机中的组件的故障而特定路径已经被锁定，则可以清除已经建立的通过网络的路径。

6. 发明授权

US5029072A Lock warning mechanism for a cache 失效
标题翻译：锁定缓存的警告机制
公开(公告)号：US5029072A
公开(公告)日：1991-07-02
申请号：US144638
申请日：1988-01-11
申请人： William C. Moyer , Ralph McGarity , James G. Gay , Jesse R. Wilson
发明人： William C. Moyer , Ralph McGarity , James G. Gay , Jesse R. Wilson
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/126
摘要： In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed using translation tables in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in the translation tables in association with the translation descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.
摘要翻译：在数据处理系统中，分页存储器管理单元（PMMU）使用由存储器中的翻译表构造的翻译器将处理器提供的逻辑地址转换为存储器中的物理地址。 PMMU在翻译缓存中维护一组最近使用的翻译器。响应于与特定页面的翻译描述符相关联的转换表中包含的特定锁定值，PMMU在与对应的翻译器相关联的翻译器缓存中设置锁定指示符，以排除在翻译器高速缓存中替换该翻译器。只要高速缓存中的预定数量的转换器都被锁定，锁定警告机制就会提供锁定警告信号。作为响应，PMMU可以警告处理器翻译器缓存有变得充满锁定的翻译器的危险。优选地，PMMU也被禁止锁定高速缓存中的最后一个转换器。

7. 发明授权

US5535398A Method and apparatus for providing both power and control by way of an integrated circuit terminal 失效
标题翻译：通过集成电路端子提供电力和控制的方法和装置
公开(公告)号：US5535398A
公开(公告)日：1996-07-09
申请号：US842951
申请日：1992-02-28
申请人： Terry L. Biggs , Donald L. Tietjen , Jesse R. Wilson
发明人： Terry L. Biggs , Donald L. Tietjen , Jesse R. Wilson
IPC分类号： G06F1/08 , G06F1/10 , G06F1/22 , H03K17/693 , G06F1/16
CPC分类号： G06F1/10 , G06F1/08 , G06F1/22 , H03K17/693
摘要： A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the multiplexer (34). The phase lock loop circuit (32) receives its power from a power and control pin (22). The multiplexer (34) receives its power from a power pin (24). The power and control pin (22) is used as a control input to multiplexer (34). Multiplexer (34) uses the power and control pin (22) to select which input to output as a system clock.
摘要翻译：一种用于通过集成电路端子（22）提供功率和控制的方法和装置。在一种形式中，时钟源（12）将周期信号提供给锁相环电路（32）和复用器（34）。锁相环电路（32）的输出是多路复用器（34）的第二输入。锁相环电路（32）从电源和控制引脚（22）接收其电力。多路复用器（34）从电源引脚（24）接收其电力。电源和控制引脚（22）用作多路复用器（34）的控制输入。多路复用器（34）使用电源和控制引脚（22）选择要作为系统时钟输出的输入。

8. 发明授权

US5015875A Toggle-free scan flip-flop 失效
标题翻译：无切换扫描触发器
公开(公告)号：US5015875A
公开(公告)日：1991-05-14
申请号：US444208
申请日：1989-12-01
申请人： Grady L. Giles , Jesse R. Wilson
发明人： Grady L. Giles , Jesse R. Wilson
IPC分类号： G06F11/267
CPC分类号： G06F11/2236
摘要： A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.
摘要翻译：提供无切换扫描触发器（TFSFF），其设计用于在测试模式扫描操作期间使用。无触发扫描触发器在测试模式扫描操作期间具有不切换其并行输出的能力。 TFSFF使用由扫描多路复用器控制的主锁存器来选择性地更新两个备用从器件锁存器。开关逻辑控制使用输入数据信号更新哪个备用从锁存器的确定。现有的扫描使能（SE）信号控制开关逻辑，因此，TFSFF设计不需要其操作的附加控制信号。在扫描测试模式期间，数据通过TFSFF从扫描数据输入端输出，并输出扫描数据输出端，而不影响系统数据输出Q.移位序列后跟一个捕获间隔，在此期间，使用所需数据自动更新Q输出以测试目标逻辑。因此，被测逻辑不受扫描测试向量的加载的影响，因为TFSFF的并行系统输出Q在移位序列期间不会切换。

9. 发明授权

US5432944A Data processing system having a dynamically enabled input synchronizer for selectively minimizing power consumption 失效
标题翻译：数据处理系统具有动态使能的输入同步器，用于选择性地最小化功耗
公开(公告)号：US5432944A
公开(公告)日：1995-07-11
申请号：US740236
申请日：1991-08-05
申请人： Charles E. Nuckolls , Donald L. Tietjen , Jesse R. Wilson
发明人： Charles E. Nuckolls , Donald L. Tietjen , Jesse R. Wilson
IPC分类号： G06F1/32 , G06F1/12 , G11C13/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1217 , Y02B60/1282
摘要： A data processor has an input synchronizer (10) which is dynamically enabled by a plurality of control signals provided by a user of the data processor. When the plurality of control signals has a predetermined logic level, a bias generator enable circuit (18) enables a bias generator (16). Subsequently, bias generator (16) enables a differential amplifier (12) to synchronize an asynchronous input signal to an operating frequency of the data processor. When the plurality of control signals does not have the predetermined logic level, bias generator enable circuit (18) disables bias generator (16). Subsequently, differential amplifier (12) is disabled and the asynchronous input is not synchronized with the internal operating frequency of the data processor. Therefore, because the user may choose the logic levels of each of the plurality of control signals, the user may dynamically disable input synchronizer (10) to minimize the power consumption of the data processor.
摘要翻译：数据处理器具有由数据处理器的用户提供的多个控制信号动态地启用的输入同步器（10）。当多个控制信号具有预定的逻辑电平时，偏置发生器使能电路（18）使能偏置发生器（16）。随后，偏置发生器（16）使差分放大器（12）能够将异步输入信号与数据处理器的工作频率同步。当多个控制信号不具有预定的逻辑电平时，偏置发生器使能电路（18）禁止偏置发生器（16）。随后，差分放大器（12）被禁用，异步输入与数据处理器的内部工作频率不同步。因此，由于用户可以选择多个控制信号中的每一个的逻辑电平，用户可以动态地禁用输入同步器（10）以最小化数据处理器的功耗。

10. 发明授权

US5003286A Binary magnitude comparator with asynchronous compare operation and method therefor 失效
标题翻译：具有异步比较运算的二进制幅度比较器及其方法
公开(公告)号：US5003286A
公开(公告)日：1991-03-26
申请号：US390556
申请日：1989-08-07
申请人： Joseph Carbonaro , R. A. Garibay, Jr. , Richard Reis , Jesse R. Wilson
发明人： Joseph Carbonaro , R. A. Garibay, Jr. , Richard Reis , Jesse R. Wilson
IPC分类号： G06F7/02 , G11C15/00 , G11C15/04
CPC分类号： G06F7/026
摘要： A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.
摘要翻译：具有多行和多列的二进制幅度比较器，包括最高有效列和最低有效列。二进制幅度比较器不是与相应位大小的时钟二进制幅度比较器在较短的时间周期内进行异步运算并进行比较。二进制幅度比较器包括形成多个行和列的多个比较器单元。每一行对应一个寄存器，每一列在该寄存器中有一个位置。通过选择具有耦合到最高有效列中的比较器单元的多个选择信号的一个或多个寄存器开始比较，并且从最高有效列继续到下一个最重要的列，并且当最不重要的比较时终止列完成。二进制幅度比较的结果是表示最高值寄存器的二进制值的第一输出信号和指示哪个行或哪一行具有最高值的第二输出信号。二进制幅度比较器被设计为以任意数量的行和列进行操作。

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