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1. 发明授权

US06766469B2 Hot-replace of memory 失效
标题翻译：热插拔内存
公开(公告)号：US06766469B2
公开(公告)日：2004-07-20
申请号：US09769783
申请日：2001-01-25
申请人： John E. Larson , John M. MacLaren , Jerome J. Johnson , Gary J. Piccirillo , Robert A. Lester , Christian H. Post , Jeffery Galloway , Anisha Anand , Ho M. Lai , Eric Rose
发明人： John E. Larson , John M. MacLaren , Jerome J. Johnson , Gary J. Piccirillo , Robert A. Lester , Christian H. Post , Jeffery Galloway , Anisha Anand , Ho M. Lai , Eric Rose
IPC分类号： G06F1100
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1044 , G06F11/1658 , G06F11/20 , G11C29/88
摘要： A method of replacing a memory module in a computer system. Specifically, a method for replacing a memory module in a segment of a redundant memory system, without powering-down the memory system.
摘要翻译：一种替换计算机系统中的存储器模块的方法。具体地说，一种用于替换冗余存储器系统的段中的存储器模块的方法，而不断电存储器系统。

2. 发明授权

US06854070B2 Hot-upgrade/hot-add memory 失效
标题翻译：热升级/热添加内存
公开(公告)号：US06854070B2
公开(公告)日：2005-02-08
申请号：US09769978
申请日：2001-01-25
申请人： Jerome J. Johnson , John M. MacLaren , Robert A. Lester , John E. Larson , Gary J. Piccirillo , Christian H. Post , Jeffery Galloway , Ho M. Lai , Anisha Anand , Eric Rose
发明人： Jerome J. Johnson , John M. MacLaren , Robert A. Lester , John E. Larson , Gary J. Piccirillo , Christian H. Post , Jeffery Galloway , Ho M. Lai , Anisha Anand , Eric Rose
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/108
摘要： A method of adding memory capacity to a computer system. The computer system comprises a redundant memory system including a plurality of memory cartridges. By powering-down a memory cartridge, adding an additional memory module to the memory cartridge, and powering-up the memory cartridge for each memory cartridge in the system, the system can transition from a redundant mode of operation to a non-redundant mode of operation for each power-down, thus allowing the computer system to remain functional during the addition of the memory module. Alternatively, memory cartridges with higher memory capacity than those currently present in the computer system can be used to replace existing memory cartridges in the computer system, using the same techniques.
摘要翻译：一种向计算机系统增加内存容量的方法。计算机系统包括包括多个存储器盒的冗余存储器系统。通过关闭存储卡，将额外的内存模块添加到内存盒，并为系统中的每个内存盒启动内存盒，系统可以从冗余操作模式转换到非冗余模式操作每个掉电，从而允许计算机系统在添加存储器模块期间保持功能。或者，可以使用具有比当前存在于计算机系统中的存储器容量更高的存储器盒来替代计算机系统中的现有存储器盒，使用相同的技术。

3. 发明授权

US06981095B1 Hot replace power control sequence logic 有权
标题翻译：热替代功率控制顺序逻辑
公开(公告)号：US06981095B1
公开(公告)日：2005-12-27
申请号：US10634576
申请日：2003-08-05
申请人： John M. MacLaren , Jerome J. Johnson , Robert A. Lester , Gary J. Piccirillo , John E. Larson , Christian H. Post , Jeffery Galloway , Ho M. Lai , Eric Rose
发明人： John M. MacLaren , Jerome J. Johnson , Robert A. Lester , Gary J. Piccirillo , John E. Larson , Christian H. Post , Jeffery Galloway , Ho M. Lai , Eric Rose
IPC分类号： G06F3/06 , G06F13/40 , G06F12/16
CPC分类号： G06F13/4081 , G06F3/0601 , G06F2003/0694
摘要： The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.
摘要翻译：用于冗余存储器系统中的热插拔存储盒的控制逻辑。为了在冗余存储器系统中实现热插拔存储器盒，提供了用于控制用于为存储器盒供电和断电的事件顺序的控制逻辑。

4. 发明授权

US06640282B2 Hot replace power control sequence logic 失效
公开(公告)号：US06640282B2
公开(公告)日：2003-10-28
申请号：US09769716
申请日：2001-01-25
申请人： John M. MacLaren , Jerome J. Johnson , Robert A. Lester , Gary J. Piccirillo , John E. Larson , Christian H. Post , Jeffery Galloway , Ho M. Lai , Eric Rose
发明人： John M. MacLaren , Jerome J. Johnson , Robert A. Lester , Gary J. Piccirillo , John E. Larson , Christian H. Post , Jeffery Galloway , Ho M. Lai , Eric Rose
IPC分类号： G06F1216
CPC分类号： G06F13/4081 , G06F3/0601 , G06F2003/0694
摘要： The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

5. 发明授权

US07028213B2 Error indication in a raid memory system 有权
公开(公告)号：US07028213B2
公开(公告)日：2006-04-11
申请号：US09965883
申请日：2001-09-28
申请人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
发明人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

6. 发明授权

US07320086B2 Error indication in a raid memory system 失效
标题翻译：突袭存储系统中的错误指示
公开(公告)号：US07320086B2
公开(公告)日：2008-01-15
申请号：US11291243
申请日：2005-12-01
申请人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
发明人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。系统实施错误中断控制，ECC错误报告，响应命令错误的墨盒错误关闭程序，每个DIMM的未使用的段中的错误信息的存储，热插拔过程指示器和存储卡和DIMM的远程标记功能。

7. 发明授权

US07010652B2 Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency 有权
标题翻译：支持非均匀内存多级条带化以最大化并发性的方法
公开(公告)号：US07010652B2
公开(公告)日：2006-03-07
申请号：US10928046
申请日：2004-08-27
申请人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
发明人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
IPC分类号： G06F12/00
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。

8. 发明授权

US06832340B2 Real-time hardware memory scrubbing 有权
标题翻译：实时硬件内存擦除
公开(公告)号：US06832340B2
公开(公告)日：2004-12-14
申请号：US09769959
申请日：2001-01-25
申请人： John E. Larson , John M. MacLaren , Robert A. Lester , Gary J. Piccirillo , Jerome J. Johnson , Patrick L. Ferguson
发明人： John E. Larson , John M. MacLaren , Robert A. Lester , Gary J. Piccirillo , Jerome J. Johnson , Patrick L. Ferguson
IPC分类号： G06F1100
CPC分类号： G06F11/1076 , G06F11/106 , G06F2211/1088
摘要： A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue. If a memory location is rewritten with new data prior to scheduled scrub corresponding to the same address location, the controller will cancel the scrub to that particular memory location.
摘要翻译：一种用于校正存储器件中的数据错误的系统和技术。更具体地，通过擦除损坏的存储器件来校正存储器件中的数据错误。通常，主机控制器将READ命令传递给存储器控制器。存储器控制器接收请求并从存储器子系统检索数据。数据传送到主机控制器。如果检测到错误，则通过存储器控制器感应擦除命令以通过存储器子系统重写校正的数据。一旦引发了一个擦除命令，一个仲裁器会调度队列中的擦除。因为在擦除写入内存之前的初始读取之前可能会发生大量时间，所以可以使用一个附加的控制器将所有后续的READ和WRITE命令与队列中调度的擦除进行比较。如果在对应于相同地址位置的计划清除之前，用新数据重写存储器位置，则控制器将取消擦除该特定存储器位置。

9. 发明授权

US06785835B2 Raid memory 有权
标题翻译：突袭记忆
公开(公告)号：US06785835B2
公开(公告)日：2004-08-31
申请号：US09769957
申请日：2001-01-25
申请人： John M. MacLaren , Paul Santeler , Kenneth A. Jansen , Sompong P. Olarig , Robert A. Lester , Patrick L. Ferguson , John E. Larson , Jerome J. Johnson , Gary J. Piccirillo
发明人： John M. MacLaren , Paul Santeler , Kenneth A. Jansen , Sompong P. Olarig , Robert A. Lester , Patrick L. Ferguson , John E. Larson , Jerome J. Johnson , Gary J. Piccirillo
IPC分类号： G06F1100
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。该系统支持具有X4和X8配置的DIMM。该系统还在各种状态之间转换，包括冗余状态和非冗余状态，以利用其可拆卸存储器盒的“热插拔”功能。

10. 发明授权

US06785785B2 Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency 有权
标题翻译：支持非均匀内存的多级剥离以最大化并发的方法
公开(公告)号：US06785785B2
公开(公告)日：2004-08-31
申请号：US09770759
申请日：2001-01-25
申请人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
发明人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
IPC分类号： G06F1200
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。

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