专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080290940A1 DIFFERENTIAL LOW NOISE AMPLIFIER (LNA) WITH COMMON MODE FEEDBACK AND GAIN CONTROL 失效
标题翻译：具有通用模式反馈和增益控制的差分低噪声放大器（LNA）
公开(公告)号：US20080290940A1
公开(公告)日：2008-11-27
申请号：US11751491
申请日：2007-05-21
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26 , H03F3/45475 , H03F3/45654 , H03F3/45748 , H03F2200/294 , H03F2203/45008 , H03F2203/45134 , H03F2203/45138 , H03F2203/45354 , H03F2203/45511 , H03F2203/45652 , H03F2203/45681 , H03G1/0029
摘要： A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a first bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.
摘要翻译：公开了一种用于低噪声放大的方法，算法，架构，电路和/或系统。在一个实施例中，放大器可以包括输入级，包括被配置为接收差分信号的第一差分输入，耦合到第一差分输入的第一电流源，接收第一偏置电压的第一电流负载并将输入级耦合到第一电源和第一对共模反馈晶体管，耦合到第一电流负载的输出并被配置为限制电流到第一电流源。输入级将放大的信号提供给具有类似于输入级的结构的附加级，被配置为进一步放大放大的信号。

2. 发明申请

US20090079499A1 Differential Low Noise Amplifier (LNA) With Common Mode Feedback And Gain Control 审中-公开
标题翻译：差分低噪声放大器（LNA），具有共模反馈和增益控制
公开(公告)号：US20090079499A1
公开(公告)日：2009-03-26
申请号：US12326318
申请日：2008-12-02
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26 , H03F3/45475 , H03F3/45654 , H03F3/45748 , H03F2200/294 , H03F2203/45008 , H03F2203/45134 , H03F2203/45138 , H03F2203/45354 , H03F2203/45511 , H03F2203/45652 , H03F2203/45681 , H03G1/0029
摘要： A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.
摘要翻译：公开了一种用于低噪声放大的方法，算法，架构，电路和/或系统。在一个实施例中，放大器可以包括输入级，包括被配置为接收差分信号的第一差分输入，耦合到第一差分输入的第一电流源，接收偏置电压的第一电流负载并将输入级耦合到第一电源和第一对共模反馈晶体管，耦合到第一电流负载的输出，并且被配置为将电流限制到第一电流源。输入级将放大的信号提供给具有类似于输入级的结构的附加级，被配置为进一步放大放大的信号。

3. 发明授权

US07471148B2 Differential low noise amplifier (LNA) with common mode feedback and gain control 失效
标题翻译：差分低噪声放大器（LNA），具有共模反馈和增益控制
公开(公告)号：US07471148B2
公开(公告)日：2008-12-30
申请号：US11751491
申请日：2007-05-21
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26 , H03F3/45475 , H03F3/45654 , H03F3/45748 , H03F2200/294 , H03F2203/45008 , H03F2203/45134 , H03F2203/45138 , H03F2203/45354 , H03F2203/45511 , H03F2203/45652 , H03F2203/45681 , H03G1/0029
摘要： A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a first bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.
摘要翻译：公开了一种用于低噪声放大的方法，算法，架构，电路和/或系统。在一个实施例中，放大器可以包括输入级，包括被配置为接收差分信号的第一差分输入，耦合到第一差分输入的第一电流源，接收第一偏置电压的第一电流负载并将输入级耦合到第一电源和第一对共模反馈晶体管，耦合到第一电流负载的输出并被配置为限制电流到第一电流源。输入级将放大的信号提供给具有类似于输入级的结构的附加级，被配置为进一步放大放大的信号。

4. 发明申请

US20070182492A1 Circuits and methods for phase locked loop lock window detection 失效
标题翻译：用于锁相环锁定窗口检测的电路和方法
公开(公告)号：US20070182492A1
公开(公告)日：2007-08-09
申请号：US11349847
申请日：2006-02-08
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03L7/085
CPC分类号： H03L7/095 , H03L7/06 , Y10S331/02
摘要： Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference clock signal, (b) a counter configured to count pulses of an output signal of the PLL (or a periodic derivative of the output signal) in response to the control signal, and (c) a decoder configured to (i) receive a counter output in response to the control signal, and (ii) produce a lock status output based on the counter output. The method generally comprises the steps of (1) counting pulses of a PLL (or a periodic derivative thereof) in response to a reference clock signal, and (2) indicating a lock status based on the number of counted pulses. The present invention advantageously provides a circuit designer the ability to tune the range of acceptable frequencies by choosing an appropriate reference frequency and adjusting the decoder to produce a positive lock status for a desired range of pulse counts.
摘要翻译：用于检测锁相环（PLL）锁定状态的电路和方法。电路通常包括：（a）控制器，被配置为响应于参考时钟信号产生控制信号，（b）计数器，被配置为对PLL的输出信号（或输出信号的周期性导数）响应于所述控制信号，以及（c）解码器，其被配置为（i）响应于所述控制信号接收计数器输出，以及（ii）基于所述计数器输出产生锁定状态输出。该方法通常包括以下步骤：（1）响应于参考时钟信号对PLL（或其周期性导数）的脉冲进行计数，以及（2）基于计数的脉冲数来指示锁定状态。本发明有利地提供电路设计者通过选择合适的参考频率来调节可接受频率的范围的能力，并且调整解码器以产生期望的脉冲计数范围的正锁定状态。

5. 发明授权

US07792514B2 Envelope detector for AM radio 失效
标题翻译： AM收音机的信封探测器
公开(公告)号：US07792514B2
公开(公告)日：2010-09-07
申请号：US11760227
申请日：2007-06-08
申请人： David Meltzer , Gregory Blum
发明人： David Meltzer , Gregory Blum
IPC分类号： H04B1/16
CPC分类号： H03D1/18 , H04B1/123
摘要： A receiver for receiving an amplitude modulated (AM) signal may include a first and a second detector for detecting the maximum and minimum envelope values, respectively, of the received AM signal and an equalizer for periodically equalizing the maximum and minimum envelope values. A method for receiving an AM signal may include unidirectionally increasing a first output signal up to the maximum envelope value, unidirectionally decreasing a second output signal down to the minimum envelope value, and periodically equalizing the first and the second output signals.
摘要翻译：用于接收幅度调制（AM）信号的接收机可以包括第一和第二检测器，用于分别检测所接收的AM信号的最大和最小包络值，以及用于周期性均衡最大和最小包络值的均衡器。用于接收AM信号的方法可以包括将第一输出信号单向增加直到最大包络值，将第二输出信号单向地减小到最小包络值，并周期性均衡第一和第二输出信号。

6. 发明申请

US20080305760A1 Envelope Detector for AM Radio 失效
标题翻译： AM无线电信封检测器
公开(公告)号：US20080305760A1
公开(公告)日：2008-12-11
申请号：US11760227
申请日：2007-06-08
申请人： David Meltzer , Gregory Blum
发明人： David Meltzer , Gregory Blum
IPC分类号： H04B1/16
CPC分类号： H03D1/18 , H04B1/123
摘要： A receiver for receiving an amplitude modulated (AM) signal may include a first and a second detector for detecting the maximum and minimum envelope values, respectively, of the received AM signal and an equalizer for periodically equalizing the maximum and minimum envelope values. A method for receiving an AM signal may include unidirectionally increasing a first output signal up to the maximum envelope value, unidirectionally decreasing a second output signal down to the minimum envelope value, and periodically equalizing the first and the second output signals.
摘要翻译：用于接收幅度调制（AM）信号的接收机可以包括第一和第二检测器，用于分别检测所接收的AM信号的最大和最小包络值，以及用于周期性均衡最大和最小包络值的均衡器。用于接收AM信号的方法可以包括将第一输出信号单向增加直到最大包络值，将第二输出信号单向地减小到最小包络值，并周期性均衡第一和第二输出信号。

7. 发明申请

US20060284670A1 Neutralization Techniques for differential low noise amplifiers 有权
标题翻译：差分低噪声放大器的中和技术
公开(公告)号：US20060284670A1
公开(公告)日：2006-12-21
申请号：US11157246
申请日：2005-06-21
申请人： Salem Eid , Gregory Blum
发明人： Salem Eid , Gregory Blum
IPC分类号： H03K5/22
CPC分类号： H03F1/26 , H03F1/14 , H03F3/191 , H03F3/45183 , H03F2200/294 , H03F2200/372 , H03F2203/45332 , H03F2203/45366 , H03F2203/45464 , H03F2203/45544 , H03F2203/45608 , H03F2203/45622 , H03F2203/45638
摘要： An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential. In this manner, similar and opposite potential differences between the gate-and-drain and the drain-and-source regions of the first input MOS transistor are reproduced in gate-and-drain and drain-and-source regions of the first neutralizing MOS transistor. A similar affect is produced in the second input and second neutralizing MOS transistor.
摘要翻译：差分LNA具有第一和第二输入MOS晶体管，其差分输入施加到其各自的控制栅极，并在其各自的漏极处获取差分输出。第二和第二输入MOS晶体管的栅极至漏极Cgd反馈电容由两个中和MOS晶体管中的相应的栅极至源极，Cgs，电容中和。第一中和MOS晶体管的控制栅极耦合到第一输入MOS晶体管的控制栅极，其源极节点耦合到第二输入MOS晶体管的漏极节点，其漏极节点耦合到固定电位。第二中和MOS晶体管的控制栅极耦合到第二输入MOS晶体管的控制栅极，其源极节点耦合到第一输入MOS晶体管的漏极节点，并且其漏极节点耦合到相同的固定电位。以这种方式，在第一中和MOS的栅极和漏极和漏极 - 源极区域中再现第一输入MOS晶体管的栅极 - 漏极和漏极 - 源极区域之间的相似和相反的电位差晶体管。在第二输入和第二中和MOS晶体管中产生类似的影响。

8. 发明申请

US20070286028A1 Radio Watch 有权
标题翻译：无线电手表
公开(公告)号：US20070286028A1
公开(公告)日：2007-12-13
申请号：US11423101
申请日：2006-06-08
申请人： David Meltzer , Gregory Blum
发明人： David Meltzer , Gregory Blum
IPC分类号： G04C11/02
CPC分类号： G04R20/10
摘要： Apparatuses, circuits, and methods for receiving at least one radio signal in a radio controlled timing apparatus using a single timing source. The present invention advantageously eliminates the need to provide an additional timing source to receive at least one radio signal, and therefore reduces the material cost and eliminates many engineering challenges.
摘要翻译：在使用单个定时源的无线电受控定时装置中接收至少一个无线电信号的装置，电路和方法。本发明有利地消除了提供附加定时源以接收至少一个无线电信号的需要，并且因此降低了材料成本并消除了许多工程挑战。

9. 发明申请

US20060198482A1 Method and apparatus for maintaining a clock/data recovery circuit frequency during transmitter low power mode 失效
标题翻译：用于在发射机低功率模式下维持时钟/数据恢复电路频率的方法和装置
公开(公告)号：US20060198482A1
公开(公告)日：2006-09-07
申请号：US11069379
申请日：2005-03-01
申请人： David Meltzer , Gregory Blum
发明人： David Meltzer , Gregory Blum
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H04L7/0083 , H04L7/033
摘要： A method, algorithm, software, architecture, circuit, and/or system for detecting an idle condition and maintaining a frequency of a clock/data recovery circuit are disclosed. In one embodiment, a method of maintaining a frequency of a clock/data recovery circuit can include the steps of: (i) comparing a difference value from a differential signal with a predetermined threshold (or value); (ii) controlling a variable frequency oscillator (VFO) with a frequency detector when the difference value is less than the threshold for at least a predetermined integration time; and (iii) controlling the VFO with a phase detector receiving the differential signal when the difference value is greater than the threshold. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for clock data recovery (CDR) circuits operable with low power mode transmitters.
摘要翻译：公开了一种用于检测空闲状态并保持时钟/数据恢复电路的频率的方法，算法，软件，架构，电路和/或系统。在一个实施例中，维持时钟/数据恢复电路的频率的方法可以包括以下步骤：（i）将差分值与差分信号与预定阈值（或值）进行比较; （ii）当所述差值小于所述阈值至少预定的积分时间时，用频率检测器控制可变频率振荡器（VFO）; 以及（iii）当差值大于阈值时，用相位检测器控制VFO接收差分信号。本发明的实施例可有利地为低功率模式发射机可操作的时钟数据恢复（CDR）电路提供可靠和简化的设计方法。

10. 发明授权

US07602258B2 Circuits, systems, and methods for a voltage controlled oscillator with coarse, fine, and center tuning 失效
标题翻译：具有粗调，精细和中心调谐的压控振荡器的电路，系统和方法
公开(公告)号：US07602258B2
公开(公告)日：2009-10-13
申请号：US11831700
申请日：2007-07-31
申请人： George Jordy , Gregory Blum
发明人： George Jordy , Gregory Blum
IPC分类号： H03K3/287 , H03K3/288
CPC分类号： H03L7/10 , H03L1/02 , H03L7/099
摘要： Circuits, systems, and methods for generating a variable oscillator output. The circuits generally comprise a capacitor configured to receive first and second currents of a first polarity (e.g., charging currents) and a third current of a second polarity opposite to the first polarity (e.g., a discharge current). The circuit further comprises a first circuit configured to receive a bias input, a second circuit configured to receive a coarse control input, and a third circuit configured to receive a fine control input. The first circuit is further configured to provide the first current in response to the bias input. The second circuit is further configured to provide the second current in response to the coarse control input, such that the second current generally has a magnitude of from zero to a multiple of the magnitude of the first current. The third circuit is further configured to provide the third current when the capacitor has a voltage that passes a threshold voltage determined by the fine control input. The present invention advantageously provides for producing a variable oscillator output over a broad range with the coarse control input, while also having low gain with the fine control input. The present invention is also advantageously suitable for standard integrated circuit manufacturing processes because the bias input can be adjusted to compensate for process variations.
摘要翻译：用于产生可变振荡器输出的电路，系统和方法。电路通常包括被配置为接收第一极性（例如，充电电流）的第一和第二电流以及与第一极性（例如，放电电流）相反的第二极性的第三电流的电容器。电路还包括被配置为接收偏置输入的第一电路，被配置为接收粗略控制输入的第二电路和被配置为接收精细控制输入的第三电路。第一电路还被配置为响应于偏置输入而提供第一电流。第二电路还被配置为响应于粗略控制输入提供第二电流，使得第二电流通常具有从零到第一电流的幅度的倍数的量值。第三电路还被配置为当电容器具有通过由精细控制输入确定的阈值电压的电压时提供第三电流。本发明有利地提供了通过粗略控制输入在宽范围内产生可变振荡器输出，同时在精细控制输入下也具有低增益。本发明还有利于标准集成电路制造工艺，因为可以调节偏置输入以补偿工艺变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式