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1. 发明申请

US20080297209A1 Circuits and Methods for Programmable Integer Clock Division with 50% Duty Cycle 失效
标题翻译：具有50％占空比的可编程整数时钟分频的电路和方法
公开(公告)号：US20080297209A1
公开(公告)日：2008-12-04
申请号：US11756461
申请日：2007-05-31
申请人： Jeremy Scuteri
发明人： Jeremy Scuteri
IPC分类号： H03K21/00
CPC分类号： H03K21/08
摘要： Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic. The present invention advantageously provides for a frequency divider structure that can be easily programmed to provide any integer divide ratio with a 50% duty cycle.
摘要翻译：电路和方法，并将输入信号的频率除以整数分频值。电路通常包括：（a）第一分频器，包括接收输入信号的第一多个串联延迟元件和第一可配置反馈网络;（b）第二分频器，包括第二多个串联连接的延迟元件，输入信号的反相和第二可配置反馈网络（c），其被配置为选择和/或组合第一和第二分频器的输出并且产生分频输出信号，以及（d）可编程电路，被配置为可选地配置第一和第二可配置反馈网络和可配置逻辑。本发明有利地提供了一种分频器结构，其可以容易地被编程以提供具有50％占空比的任何整数除法比。

2. 发明授权

US07505548B2 Circuits and methods for programmable integer clock division with 50% duty cycle 失效
标题翻译：具有50％占空比的可编程整数时钟分频的电路和方法
公开(公告)号：US07505548B2
公开(公告)日：2009-03-17
申请号：US11756461
申请日：2007-05-31
申请人： Jeremy Scuteri
发明人： Jeremy Scuteri
IPC分类号： H03K21/00
CPC分类号： H03K21/08
摘要： Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic. The present invention advantageously provides for a frequency divider structure that can be easily programmed to provide any integer divide ratio with a 50% duty cycle.
摘要翻译：电路和方法，并将输入信号的频率除以整数分频值。电路通常包括：（a）第一分频器，包括接收输入信号的第一多个串联延迟元件和第一可配置反馈网络;（b）第二分频器，包括第二多个串联连接的延迟元件，输入信号的反相和第二可配置反馈网络（c），其被配置为选择和/或组合第一和第二分频器的输出并且产生分频输出信号，以及（d）可编程电路，被配置为可选地配置第一和第二可配置反馈网络和可配置逻辑。本发明有利地提供了一种分频器结构，其可以容易地被编程以提供具有50％占空比的任何整数除法比。

3. 发明申请

US20080290940A1 DIFFERENTIAL LOW NOISE AMPLIFIER (LNA) WITH COMMON MODE FEEDBACK AND GAIN CONTROL 失效
标题翻译：具有通用模式反馈和增益控制的差分低噪声放大器（LNA）
公开(公告)号：US20080290940A1
公开(公告)日：2008-11-27
申请号：US11751491
申请日：2007-05-21
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26 , H03F3/45475 , H03F3/45654 , H03F3/45748 , H03F2200/294 , H03F2203/45008 , H03F2203/45134 , H03F2203/45138 , H03F2203/45354 , H03F2203/45511 , H03F2203/45652 , H03F2203/45681 , H03G1/0029
摘要： A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a first bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.
摘要翻译：公开了一种用于低噪声放大的方法，算法，架构，电路和/或系统。在一个实施例中，放大器可以包括输入级，包括被配置为接收差分信号的第一差分输入，耦合到第一差分输入的第一电流源，接收第一偏置电压的第一电流负载并将输入级耦合到第一电源和第一对共模反馈晶体管，耦合到第一电流负载的输出并被配置为限制电流到第一电流源。输入级将放大的信号提供给具有类似于输入级的结构的附加级，被配置为进一步放大放大的信号。

4. 发明申请

US20090079499A1 Differential Low Noise Amplifier (LNA) With Common Mode Feedback And Gain Control 审中-公开
标题翻译：差分低噪声放大器（LNA），具有共模反馈和增益控制
公开(公告)号：US20090079499A1
公开(公告)日：2009-03-26
申请号：US12326318
申请日：2008-12-02
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26 , H03F3/45475 , H03F3/45654 , H03F3/45748 , H03F2200/294 , H03F2203/45008 , H03F2203/45134 , H03F2203/45138 , H03F2203/45354 , H03F2203/45511 , H03F2203/45652 , H03F2203/45681 , H03G1/0029
摘要： A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.
摘要翻译：公开了一种用于低噪声放大的方法，算法，架构，电路和/或系统。在一个实施例中，放大器可以包括输入级，包括被配置为接收差分信号的第一差分输入，耦合到第一差分输入的第一电流源，接收偏置电压的第一电流负载并将输入级耦合到第一电源和第一对共模反馈晶体管，耦合到第一电流负载的输出，并且被配置为将电流限制到第一电流源。输入级将放大的信号提供给具有类似于输入级的结构的附加级，被配置为进一步放大放大的信号。

5. 发明授权

US07471148B2 Differential low noise amplifier (LNA) with common mode feedback and gain control 失效
标题翻译：差分低噪声放大器（LNA），具有共模反馈和增益控制
公开(公告)号：US07471148B2
公开(公告)日：2008-12-30
申请号：US11751491
申请日：2007-05-21
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26 , H03F3/45475 , H03F3/45654 , H03F3/45748 , H03F2200/294 , H03F2203/45008 , H03F2203/45134 , H03F2203/45138 , H03F2203/45354 , H03F2203/45511 , H03F2203/45652 , H03F2203/45681 , H03G1/0029
摘要： A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a first bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.
摘要翻译：公开了一种用于低噪声放大的方法，算法，架构，电路和/或系统。在一个实施例中，放大器可以包括输入级，包括被配置为接收差分信号的第一差分输入，耦合到第一差分输入的第一电流源，接收第一偏置电压的第一电流负载并将输入级耦合到第一电源和第一对共模反馈晶体管，耦合到第一电流负载的输出并被配置为限制电流到第一电流源。输入级将放大的信号提供给具有类似于输入级的结构的附加级，被配置为进一步放大放大的信号。

6. 发明授权

US07317359B2 Circuits and methods for phase locked loop lock window detection 失效
标题翻译：用于锁相环锁定窗口检测的电路和方法
公开(公告)号：US07317359B2
公开(公告)日：2008-01-08
申请号：US11349847
申请日：2006-02-08
申请人： Jeremy Scuteri , Gregory A. Blum
发明人： Jeremy Scuteri , Gregory A. Blum
IPC分类号： H03L7/089
CPC分类号： H03L7/095 , H03L7/06 , Y10S331/02
摘要： Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference clock signal, (b) a counter configured to count pulses of an output signal of the PLL (or a periodic derivative of the output signal) in response to the control signal, and (c) a decoder configured to (i) receive a counter output in response to the control signal, and (ii) produce a lock status output based on the counter output. The method generally comprises the steps of (1) counting pulses of a PLL (or a periodic derivative thereof) in response to a reference clock signal, and (2) indicating a lock status based on the number of counted pulses. The present invention advantageously provides a circuit designer the ability to tune the range of acceptable frequencies by choosing an appropriate reference frequency and adjusting the decoder to produce a positive lock status for a desired range of pulse counts.
摘要翻译：用于检测锁相环（PLL）锁定状态的电路和方法。电路通常包括：（a）控制器，被配置为响应于参考时钟信号产生控制信号，（b）计数器，被配置为对PLL的输出信号（或输出信号的周期性导数）响应于所述控制信号，以及（c）解码器，其被配置为（i）响应于所述控制信号接收计数器输出，以及（ii）基于所述计数器输出产生锁定状态输出。该方法通常包括以下步骤：（1）响应于参考时钟信号对PLL（或其周期性导数）的脉冲进行计数，以及（2）基于计数的脉冲数来指示锁定状态。本发明有利地提供电路设计者通过选择合适的参考频率来调节可接受频率的范围的能力，并且调整解码器以产生期望的脉冲计数范围的正锁定状态。

7. 发明申请

US20070182492A1 Circuits and methods for phase locked loop lock window detection 失效
标题翻译：用于锁相环锁定窗口检测的电路和方法
公开(公告)号：US20070182492A1
公开(公告)日：2007-08-09
申请号：US11349847
申请日：2006-02-08
申请人： Jeremy Scuteri , Gregory Blum
发明人： Jeremy Scuteri , Gregory Blum
IPC分类号： H03L7/085
CPC分类号： H03L7/095 , H03L7/06 , Y10S331/02
摘要： Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference clock signal, (b) a counter configured to count pulses of an output signal of the PLL (or a periodic derivative of the output signal) in response to the control signal, and (c) a decoder configured to (i) receive a counter output in response to the control signal, and (ii) produce a lock status output based on the counter output. The method generally comprises the steps of (1) counting pulses of a PLL (or a periodic derivative thereof) in response to a reference clock signal, and (2) indicating a lock status based on the number of counted pulses. The present invention advantageously provides a circuit designer the ability to tune the range of acceptable frequencies by choosing an appropriate reference frequency and adjusting the decoder to produce a positive lock status for a desired range of pulse counts.
摘要翻译：用于检测锁相环（PLL）锁定状态的电路和方法。电路通常包括：（a）控制器，被配置为响应于参考时钟信号产生控制信号，（b）计数器，被配置为对PLL的输出信号（或输出信号的周期性导数）响应于所述控制信号，以及（c）解码器，其被配置为（i）响应于所述控制信号接收计数器输出，以及（ii）基于所述计数器输出产生锁定状态输出。该方法通常包括以下步骤：（1）响应于参考时钟信号对PLL（或其周期性导数）的脉冲进行计数，以及（2）基于计数的脉冲数来指示锁定状态。本发明有利地提供电路设计者通过选择合适的参考频率来调节可接受频率的范围的能力，并且调整解码器以产生期望的脉冲计数范围的正锁定状态。

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