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1. 发明申请

US20090090955A1 ELEVATED CHANNEL FLASH DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：高通道闪光器件及其制造方法
公开(公告)号：US20090090955A1
公开(公告)日：2009-04-09
申请号：US12057391
申请日：2008-03-28
申请人： Jer-Chyi Wang , Ming-Cheng Chang , Yi-Feng Chang , Wei-Ming Liao , Chien-Chang Huang
发明人： Jer-Chyi Wang , Ming-Cheng Chang , Yi-Feng Chang , Wei-Ming Liao , Chien-Chang Huang
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7887 , H01L29/40114 , H01L29/66825 , H01L29/7851
摘要： A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density.
摘要翻译：一种闪存装置，其特征在于，具备：一体地形成有突出部的基板，两个浮置栅极，控制栅极和电介质层。两个浮动门设置在突出部分的两侧并分别覆盖突出部分的一部分。控制门设置在突出部分的顶部并夹在两个浮动门之间。介电层设置在两个浮动栅极和控制栅极之间。因为FLASH装置的控制门设置在突出部分上，所以可以形成升高的通道。此外，由于两个浮栅的位置，可以增加有效浮栅（FG）长度而不影响单元密度。

2. 发明申请

US20090085089A1 TWO-BIT FLASH MEMORY 有权
标题翻译：两位闪存
公开(公告)号：US20090085089A1
公开(公告)日：2009-04-02
申请号：US12099168
申请日：2008-04-08
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L29/42336
摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.
摘要翻译：闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。突出部从基板的顶面延伸。控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。电介质层夹在控制栅极和两个浮栅之中。由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

3. 发明申请

US20080283904A1 TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：双位闪存存储器单元及其制造方法
公开(公告)号：US20080283904A1
公开(公告)日：2008-11-20
申请号：US11828334
申请日：2007-07-25
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
IPC分类号： H01L29/792
CPC分类号： H01L29/7887 , H01L29/40114
摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate.
摘要翻译：两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，堆叠在栅极氧化物层上的栅极。电荷存储间隔堆叠设置在栅极的任一侧。电荷存储间隔堆叠包括底部电荷存储层和上部间隔层。绝缘层设置在电荷存储间隔堆叠和栅极之间。衬底设置在底部电荷存储层下面。源极/漏极区域设置在衬底内的底部电荷存储层的一侧。

4. 发明授权

US07956403B2 Two-bit flash memory 有权
标题翻译：两位闪存
公开(公告)号：US07956403B2
公开(公告)日：2011-06-07
申请号：US12099168
申请日：2008-04-08
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L29/42336
摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.
摘要翻译：闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。突出部从基板的顶面延伸。控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。电介质层夹在控制栅极和两个浮栅之中。由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

5. 发明申请

US20090108321A1 FLASH MEMORY 审中-公开
标题翻译：闪存
公开(公告)号：US20090108321A1
公开(公告)日：2009-04-30
申请号：US11948947
申请日：2007-11-30
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , H01L29/40114 , H01L29/42324 , H01L29/7887
摘要： A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate.
摘要翻译：提供闪存。闪速存储器包括基板，形成在基板上的第一绝缘层，设置在第一绝缘层上的控制栅极和与分别设置在控制栅极两侧的基板共面的两个浮动栅极。

6. 发明申请

US20080265342A1 TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：双位闪存存储器单元及其制造方法
公开(公告)号：US20080265342A1
公开(公告)日：2008-10-30
申请号：US11780482
申请日：2007-07-20
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7923 , H01L29/40117 , H01L29/42348
摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate.
摘要翻译：两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，栅极氧化物层上的T形栅极。第一电荷存储层设置在T形门的一侧和下方。通过T形栅极和栅极氧化物层的底部与第一电荷存储层分离的第二电荷存储层设置在T形栅极的另一侧和下方。绝缘层设置在T形栅极和栅极氧化物层之间。第一源极/漏极区域设置在衬底内的T形栅极的一侧。第二源极/漏极区域设置在衬底内的T形栅极的另一侧。

7. 发明申请

US20090020801A1 TWO-BIT FLASH MEMORY CELL STRUCTURE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：双位闪存存储器单元结构及其制造方法
公开(公告)号：US20090020801A1
公开(公告)日：2009-01-22
申请号：US11951344
申请日：2007-12-06
申请人： Wei-Ming Liao , Ming-Cheng Chang , Jer-Chyi Wang
发明人： Wei-Ming Liao , Ming-Cheng Chang , Jer-Chyi Wang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7887 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P+ source/drain region next to the spacer, and an N+ pocket region encompassing the P+ source/drain region and covering the area directly under the floating gate.
摘要翻译：闪存单元包括衬底上的控制栅极氧化层，控制栅极氧化层上的T形控制栅极，设置在T形控制栅极的两个凹入侧壁上的浮置栅极，控制栅极之间的绝缘层浮置栅极和浮置栅极之间的电介质层，浮置栅极的侧壁上的间隔物，隔着间隔物的P +源极/漏极区域和包围P +源极/漏极区域的N +穴状区域，以及覆盖浮动门下方的区域。

8. 发明申请

US20090047764A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090047764A1
公开(公告)日：2009-02-19
申请号：US11953076
申请日：2007-12-10
申请人： Wei-Ming Liao , Ming-Cheng Chang , Chien-Chang Huang
发明人： Wei-Ming Liao , Ming-Cheng Chang , Chien-Chang Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11521
摘要： A non-volatile memory having a gate structure and a source/drain region is provided. The gate structure is disposed on a substrate. The gate structure includes a pair of floating gates, tunneling dielectric layers, a control gate and an inter-gate dielectric layer. The floating gates are disposed on the substrate. Each tunneling dielectric layer is disposed between each floating gate and the substrate. The control gate is disposed on the substrate between the pair of the floating gates and covers a top surface and sidewalls of each floating gate. The inter-gate dielectric layer is disposed between the control gate and each of the floating gates, disposed between the control gate and each of the tunneling dielectric layers, and disposed between the control gate and the substrate. The source/drain region is disposed in the substrate at respective sides of the gate structure.
摘要翻译：提供具有栅极结构和源极/漏极区域的非易失性存储器。栅极结构设置在基板上。栅极结构包括一对浮置栅极，隧道电介质层，控制栅极和栅极间介电层。浮置栅极设置在基板上。每个隧道介电层设置在每个浮动栅极和衬底之间。控制栅极设置在一对浮置栅极之间的衬底上并且覆盖每个浮动栅极的顶表面和侧壁。栅极间电介质层设置在控制栅极和每个浮置栅极之间，设置在控制栅极和每个隧道介电层之间，并且设置在控制栅极和衬底之间。源极/漏极区域在栅极结构的相应侧设置在衬底中。

9. 发明授权

US07667262B2 Two bit U-shaped memory structure and method of making the same 有权
标题翻译：两位U形记忆体结构及制作方法
公开(公告)号：US07667262B2
公开(公告)日：2010-02-23
申请号：US12139499
申请日：2008-06-15
申请人： Wei-Ming Liao , Jer-Chyi Wang
发明人： Wei-Ming Liao , Jer-Chyi Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/1037 , H01L29/1041 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.
摘要翻译：存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

10. 发明申请

US20090256189A1 TWO BIT U-SHAPED MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：两位U形存储器结构及其制造方法
公开(公告)号：US20090256189A1
公开(公告)日：2009-10-15
申请号：US12139499
申请日：2008-06-15
申请人： Wei-Ming Liao , Jer-Chyi Wang
发明人： Wei-Ming Liao , Jer-Chyi Wang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/1037 , H01L29/1041 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.
摘要翻译：存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

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