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1. 发明授权

US08169835B2 Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer 有权
标题翻译：具有带氮工程隧穿结构的电荷捕获存储单元与氧氮化物隔离层
公开(公告)号：US08169835B2
公开(公告)日：2012-05-01
申请号：US12568272
申请日：2009-09-28
申请人： Jeng-Hwa Liao , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： G11C16/04
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/792
摘要： A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.
摘要翻译：带隙设计的电荷捕获存储单元包括包含俘获层的电荷存储结构。阻挡层和包括薄隧穿层，薄带隙偏移层和包含氮氧化硅的薄隔离层的介电隧道结构。使用低热预算过程制造存储器单元。

2. 发明申请

US20110075486A1 CHARGE TRAPPING MEMORY CELL HAVING BANDGAP ENGINEERED TUNNELING STRUCTURE WITH OXYNITRIDE ISOLATION LAYER 有权
标题翻译：带有氧化物隔离层的带状工程隧道结构的电荷捕获存储单元
公开(公告)号：US20110075486A1
公开(公告)日：2011-03-31
申请号：US12568272
申请日：2009-09-28
申请人： Jeng-Hwa Liao , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： G11C16/04 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/792
摘要： A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.
摘要翻译：带隙设计的电荷捕获存储单元包括包含俘获层的电荷存储结构。阻挡层和包括薄隧穿层，薄带隙偏移层和包含氮氧化硅的薄隔离层的介电隧道结构。使用低热预算过程制造存储器单元。

3. 发明申请

US20070287260A1 METHODS FOR FORMING AN ISOLATION STRUCTURE IN A SILICON SUBSTRATE 有权
标题翻译：在硅衬底中形成隔离结构的方法
公开(公告)号：US20070287260A1
公开(公告)日：2007-12-13
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

4. 发明授权

US07442620B2 Methods for forming a trench isolation structure with rounded corners in a silicon substrate 有权
标题翻译：在硅衬底中形成具有圆角的沟槽隔离结构的方法
公开(公告)号：US07442620B2
公开(公告)日：2008-10-28
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

5. 发明申请

US20090114973A1 METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS SIMULTANEOUSLY 有权
标题翻译：同时形成自对准联系人和本地互连的方法
公开(公告)号：US20090114973A1
公开(公告)日：2009-05-07
申请号：US12113855
申请日：2008-05-01
申请人： Tuung Luoh , Ling-Wuu Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wuu Yang , Kuang-Chao Chen
IPC分类号： H01L29/788 , H01L23/52
CPC分类号： H01L27/11521 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.
摘要翻译：本发明一般涉及半导体，更具体地涉及半导体存储器件结构和改进的制造方法。改进的制造工艺允许自对准触点和局部互连同时处理。该过程允许自对准触点和局部互连之间的最小距离要求加宽，这使得自对准触点和局部互连的图案化变得更容易。扩大的最小距离要求也允许进一步的记忆体细胞收缩。自对准触点和局部互连的改进结构也具有优异的隔离特性。

6. 发明申请

US20090081859A1 Metallization process 审中-公开
标题翻译：金属化过程
公开(公告)号：US20090081859A1
公开(公告)日：2009-03-26
申请号：US11902228
申请日：2007-09-20
申请人： Tuung Luoh , Ling-Wuu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wuu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28518 , H01L29/665 , H01L29/7833
摘要： A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region.
摘要翻译：提供金属化工艺。金属化处理包括以下步骤。首先，提供至少具有含硅导电区域的半导体基底。之后，将氮离子注入含硅导电区域。接下来，对半导体基板进行第一热处理，以修复半导体基底的表面。然后，在半导体基底的表面上形成金属层，并且金属层覆盖含硅导电区域。最后，在覆盖有金属层的半导体基底上进行第二热处理，以在含硅导电区域上形成金属硅化物层。

7. 发明申请

US20070212833A1 Methods for making a nonvolatile memory device comprising a shunt silicon layer 审中-公开
标题翻译：用于制造包括分流硅层的非易失性存储器件的方法
公开(公告)号：US20070212833A1
公开(公告)日：2007-09-13
申请号：US11374337
申请日：2006-03-13
申请人： Chi-Pin Lu , Ling-Wuu Yang , Kuang-Chao Chen
发明人： Chi-Pin Lu , Ling-Wuu Yang , Kuang-Chao Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/11568
摘要： A nitride read only memory comprises a selectively grown, epitaxial, shunt silicon layer (shunt layer) that reduces the bit line sheet resistance and increases bit line mobility. The shunt layer can be grown by a in situ, P-doped deposit at high temperature. A bit line interface without native oxide and excellent electron mobility can be achieved using the methods for selective epitaxial growth described herein.
摘要翻译：氮化物只读存储器包括选择性地生长的外延并联硅层（分流层），其减少位线片电阻并增加位线移动性。分流层可以通过原位，P掺杂的沉积物在高温下生长。可以使用本文所述的用于选择性外延生长的方法来实现不具有天然氧化物和优异的电子迁移率的位线界面。

8. 发明申请

US20050064713A1 [METHOD OF FABRICATING FLASH MEMORY] 有权
标题翻译： [制作闪速存储器的方法]
公开(公告)号：US20050064713A1
公开(公告)日：2005-03-24
申请号：US10605255
申请日：2003-09-18
申请人： Kuang-Chao Chen , Jui-Lin Lu , Ling-Wuu Yang
发明人： Kuang-Chao Chen , Jui-Lin Lu , Ling-Wuu Yang
IPC分类号： H01L21/302 , H01L21/311 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.
摘要翻译：在制造闪速存储器的方法中，在衬底上依次形成隧道电介质层，第一导电层和掩模层，以形成栅极结构。然后在条带之间的衬底中形成埋入的源极/漏极区域。条带进一步图案化为浮动栅极结构。绝缘层形成为与栅极结构相邻的侧面。绝缘层具有比栅极结构的第一导电层的顶表面低的顶表面。去除掩模层，并且在第一导电层上形成一个额外的导电层，以便在相邻的绝缘层上延伸。第一和另外的导电层形成浮栅。栅极电介质层形成在浮栅上，在栅介电层上形成控制栅极。

9. 发明授权

US08581322B2 Nonvolatile memory device and method for making the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08581322B2
公开(公告)日：2013-11-12
申请号：US13170618
申请日：2011-06-28
申请人： Chi-Pin Lu , Jung-Yu Hsieh , Ling-Wuu Yang
发明人： Chi-Pin Lu , Jung-Yu Hsieh , Ling-Wuu Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521
摘要： A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface.
摘要翻译：一种制造非易失性存储器件的方法包括以下步骤。形成导电结构，其中导电结构具有第一顶部部分。第一顶部部分被转换成具有圆顶表面的第二顶部部分。

10. 发明授权

US07517780B2 Method for eliminating polycide voids through nitrogen implantation 有权
标题翻译：通过氮气注入消除多孔化合物空隙的方法
公开(公告)号：US07517780B2
公开(公告)日：2009-04-14
申请号：US11044212
申请日：2005-01-28
申请人： Ling-Wuu Yang , Kuang-Chao Chen , Tuung Luoh
发明人： Ling-Wuu Yang , Kuang-Chao Chen , Tuung Luoh
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/32155 , H01L29/66575
摘要： A method of manufacturing a semiconductor device includes providing a first layer over a wafer substrate, providing a polysilicon layer over the first layer, implanting nitrogen ions into the polysilicon layer, forming a polycide layer over the polysilicon layer, and forming source and drain regions.
摘要翻译：一种制造半导体器件的方法包括在晶片衬底上提供第一层，在第一层上提供多晶硅层，将氮离子注入到多晶硅层中，在多晶硅层上形成多晶硅化物层，以及形成源区和漏极区。

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