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1. 发明授权

US5972798A Prevention of die loss to chemical mechanical polishing 失效
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US5972798A
公开(公告)日：1999-10-26
申请号：US86775
申请日：1998-05-29
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

2. 发明授权

US06444371B1 Prevention of die loss to chemical mechanical polishing 有权
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US06444371B1
公开(公告)日：2002-09-03
申请号：US09377541
申请日：1999-08-19
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

3. 发明授权

US5933744A Alignment method for used in chemical mechanical polishing process 失效
标题翻译：用于化学机械抛光工艺的对准方法
公开(公告)号：US5933744A
公开(公告)日：1999-08-03
申请号：US54302
申请日：1998-04-02
申请人： Jeng-Horng Chen , Tsu Shih , Jui-Yu Chang , Chung-Long Chang
发明人： Jeng-Horng Chen , Tsu Shih , Jui-Yu Chang , Chung-Long Chang
IPC分类号： H01L21/3105 , H01L23/544 , H01L21/465 , H01L21/76
CPC分类号： H01L23/544 , H01L21/31053 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.
摘要翻译：用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。第一介电层沉积在晶片上用于隔离。然后，使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。在第一电介质层中形成第一导电插塞。接下来，在第一电介质层的表面和钨插塞上形成第一导电层。因此，第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。接下来，在第二导电层的表面上形成第二非零对准标记图案，并与第二导电插塞对准。通过重复上述方法，将在第一非零对准标记图案上形成奇数非零对准标记图案，并且甚至在第二非零对准标记图案上形成非零对准标记图案。因此，本发明节省空间，将非零对准标记放置在多层互连和平面化处理中。

4. 发明授权

US5919714A Segmented box-in-box for improving back end overlay measurement 失效
公开(公告)号：US5919714A
公开(公告)日：1999-07-06
申请号：US72990
申请日：1998-05-06
申请人： Jeng-Horng Chen , Tsu Shih
发明人： Jeng-Horng Chen , Tsu Shih
IPC分类号： G03F7/20 , H01L21/00
CPC分类号： G03F7/70633 , Y10S438/975
摘要： An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.

5. 发明授权

US6118185A Segmented box-in-box for improving back end overlay measurement 有权
标题翻译：分段盒装盒，用于改进后端重叠测量
公开(公告)号：US6118185A
公开(公告)日：2000-09-12
申请号：US262303
申请日：1999-03-04
申请人： Jeng-Horng Chen , Tsu Shih
发明人： Jeng-Horng Chen , Tsu Shih
IPC分类号： G03F7/20 , H01L23/544 , H01L21/46 , H01L21/76 , H01L21/78 , H01L23/58
CPC分类号： G03F7/70633 , Y10S438/975
摘要： An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.
摘要翻译：通过从包括从沟槽的底部向上突出的多个同心脊组成的分段沟槽形成外盒已经实现了箱内叠加测量方法的改进。当分段的沟槽已经用钨（或类似的金属）过量填充时，使用回蚀或化学去除多余的金属。机械抛光作为平面化技术。由于脊的存在，当内盒（将从第一层沉积的第二层蚀刻时）位于其内部时，沟槽（即外盒）变得可再现地容易看到。此外，现在很大程度上消除了外箱在关键位置的破坏（通常在现有技术中看到）的倾向。

6. 发明申请

US20140038107A1 Method and System for E-Beam Lithography with Multi-Exposure 有权
标题翻译：多重曝光电子束平版印刷方法与系统
公开(公告)号：US20140038107A1
公开(公告)日：2014-02-06
申请号：US13562877
申请日：2012-07-31
申请人： Pei-Shiang Chen , Hung-Chun Wang , Jeng-Horng Chen
发明人： Pei-Shiang Chen , Hung-Chun Wang , Jeng-Horng Chen
IPC分类号： G03F7/20 , G21K5/08
CPC分类号： H01L21/3083 , B82Y10/00 , B82Y40/00 , G03F7/2037 , H01J37/3174 , H01J2237/30488 , H01J2237/3175 , H01J2237/31761 , H01J2237/31774
摘要： The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.
摘要翻译：本公开提供了一种用于电子束（e-beam）光刻图案化的方法。该方法包括在基板上形成抗蚀剂层; 根据第一图案对抗蚀剂层进行第一电子束曝光处理; 根据第二图案对抗蚀剂层进行第二电子束曝光处理，其中第二图案化与抗蚀剂层上的第一图案重叠; 并显影抗蚀剂层。

7. 发明申请

US20130320243A1 EFFICIENT SCAN FOR E-BEAM LITHOGRAPHY 有权
标题翻译： E-BEAM LITHOGRAPHY的高效扫描
公开(公告)号：US20130320243A1
公开(公告)日：2013-12-05
申请号：US13484524
申请日：2012-05-31
申请人： Cheng-Hung Chen , Shih-Chi Wang , Jeng-Horng Chen , Burn Jeng Lin
发明人： Cheng-Hung Chen , Shih-Chi Wang , Jeng-Horng Chen , Burn Jeng Lin
IPC分类号： G21K5/10
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J2237/31761
摘要： The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.
摘要翻译：本公开提供了一种通过电子束光刻系统增加晶片通过量的方法。该方法包括使用电子束写入器的最大扫描狭缝宽度（MSSW）扫描晶片。通过限制集成电路（IC）场尺寸以允许MSSW覆盖整个场，MSSW被应用于减小晶片的扫描通道，从而增加吞吐量。当用MSSW扫描晶片时，下一个扫描通道数据可以重新排列并加载到存储器缓冲器中。因此，一旦一个扫描通道完成，读取存储器缓冲器中的下一个扫描通道数据进行扫描。

8. 发明授权

US08563224B1 Data process for E-beam lithography 有权
标题翻译：电子束光刻数据处理
公开(公告)号：US08563224B1
公开(公告)日：2013-10-22
申请号：US13487850
申请日：2012-06-04
申请人： Cheng-Hung Chen , Pei-Shiang Chen , Shih-Chi Wang , Jeng-Horng Chen
发明人： Cheng-Hung Chen , Pei-Shiang Chen , Shih-Chi Wang , Jeng-Horng Chen
IPC分类号： G03C5/00 , G03F1/20
CPC分类号： G06F17/50 , G03C5/00 , G03F1/20 , H01J2237/31762 , H01J2237/31764 , H01J2237/31769 , Y10S430/143
摘要： The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.
摘要翻译：本公开提供了通过电子束光刻系统增加晶片生产量的抖动方法。抖动方法从顶点图生成边缘图。顶点图是从集成电路设计布局（如原始图案位图）生成的。也从集成电路设计布局生成灰色地图（也称为图案灰度图）。通过将边缘图与灰度图组合，生成修改后的集成电路设计布局（修改图案位图），供电子束光刻系统使用。

9. 发明授权

US07659964B2 Level adjustment systems and adjustable pin chuck thereof 失效
标题翻译：液位调节系统及其可调针式卡盘
公开(公告)号：US07659964B2
公开(公告)日：2010-02-09
申请号：US11390944
申请日：2006-03-28
申请人： Burn-Jeng Lin , Tsai-Sheng Gau , Jeng-Horng Chen
发明人： Burn-Jeng Lin , Tsai-Sheng Gau , Jeng-Horng Chen
IPC分类号： G03B27/58
CPC分类号： H01L21/6838 , H01L21/67259 , H01L21/67288 , H01L21/68742
摘要： A level adjustment system. The level adjustment system includes an adjustable pin chuck, an evacuation device, a level detection device and a length control device. The adjustable pin chuck includes a base and a variable pin to support a substrate. The base includes a recess and an evacuation channel connected thereto. The variable pin is disposed in the recess. The evacuation device is connected to the evacuation channel to evacuate the recess, such that the substrate is attached to the base and variable pin. The level detection device is disposed on the adjustable pin chuck to detect the horizontality of a target surface of the substrate. The length control device is electrically connected to the level detection device and variable pin. The length control device changes the length of the variable pin to adjust level of the target surface of the substrate according to the detected horizontality.
摘要翻译：水平调整系统。液位调节系统包括可调节销卡盘，排气装置，液位检测装置和长度控制装置。可调销卡盘包括基座和可变销以支撑基板。基座包括与其连接的凹部和排气通道。可变销设置在凹槽中。排气装置连接到排气通道以排出凹部，使得基板附接到基座和可变销。电平检测装置设置在可调节销卡盘上以检测基板的目标表面的水平度。长度控制装置电连接到电平检测装置和可变引脚。长度控制装置根据检测到的水平度改变可变销的长度，以调整基板的目标表面的水平。

10. 发明申请

US20090268184A1 System and Method for Direct Writing to a Wafer 有权
标题翻译：直接写入晶片的系统和方法
公开(公告)号：US20090268184A1
公开(公告)日：2009-10-29
申请号：US12203494
申请日：2008-09-03
申请人： Burn Jeng Lin , Jeng-Horng Chen , Shy-Jay Lin , Tsai-Sheng Gau
发明人： Burn Jeng Lin , Jeng-Horng Chen , Shy-Jay Lin , Tsai-Sheng Gau
IPC分类号： G03B27/54
CPC分类号： G03F7/70383 , B82Y10/00 , B82Y40/00 , H01J37/3174
摘要： A direct-write (DW) exposure system is provided which includes a stage for holding a substrate and configured to scan the substrate along an axis during exposure, a data processing module for processing pattering data and generating instructions associated with the patterning data, and an exposure module that includes a plurality of beams that are focused onto the substrate such that the beams cover a width that is larger than a width of a field size and a beam controller that controls the plurality of beams in accordance with the instructions as the substrate is scanned along the axis. The widths are in a direction different from the axis.
摘要翻译：提供了一种直接写入（DW）曝光系统，其包括用于保持衬底并被配置为在曝光期间沿着轴扫描衬底的台，用于处理图案数据并产生与图案形成数据相关联的指令的数据处理模块，以及曝光模块，其包括聚焦在基板上的多个光束，使得光束覆盖大于场大小的宽度的宽度;以及根据作为衬底的指令来控制多个光束的光束控制器沿轴扫描。宽度在与轴不同的方向。

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