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1. 发明授权

US08921977B2 Capacitor array and method of fabricating the same 有权
标题翻译：电容阵列及其制造方法
公开(公告)号：US08921977B2
公开(公告)日：2014-12-30
申请号：US13333564
申请日：2011-12-21
申请人： Jen Jui Huang , Che Chi Lee , Shih Shu Tsai , Cheng Shun Chen , Shao Ta Hsu , Chao Wen Lay , Chun I Hsieh , Ching Kai Lin
发明人： Jen Jui Huang , Che Chi Lee , Shih Shu Tsai , Cheng Shun Chen , Shao Ta Hsu , Chao Wen Lay , Chun I Hsieh , Ching Kai Lin
IPC分类号： H01L29/92 , H01L27/108 , H01L27/105
CPC分类号： H01L27/10817 , H01L27/105 , H01L27/10852 , H01L28/91
摘要： A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
摘要翻译：电容器阵列包括多个电容器和支撑框架。每个电容器包括电极。支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。每个支撑结构可以围绕相应的电极。支撑框架可以包括掺杂可氧化材料的氧化物。

2. 发明申请

US20130161786A1 CAPACITOR ARRAY AND METHOD OF FABRICATING THE SAME 有权
标题翻译：电容阵列及其制造方法
公开(公告)号：US20130161786A1
公开(公告)日：2013-06-27
申请号：US13333564
申请日：2011-12-21
申请人： Jen Jui Huang , Che Chi Lee , Shih Shu Tsai , Cheng Shun Chen , Shao Ta Hsu , Chao Wen Lay , Chun I. Hsieh , Ching Kai Lin
发明人： Jen Jui Huang , Che Chi Lee , Shih Shu Tsai , Cheng Shun Chen , Shao Ta Hsu , Chao Wen Lay , Chun I. Hsieh , Ching Kai Lin
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10817 , H01L27/105 , H01L27/10852 , H01L28/91
摘要： A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
摘要翻译：电容器阵列包括多个电容器和支撑框架。每个电容器包括电极。支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。每个支撑结构可以围绕相应的电极。支撑框架可以包括掺杂可氧化材料的氧化物。

3. 发明授权

US08497541B2 Memory having buried digit lines and methods of making the same 有权
标题翻译：具有埋置数字线的存储器和制作相同的方法
公开(公告)号：US08497541B2
公开(公告)日：2013-07-30
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

4. 发明申请

US20110220980A1 MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME 有权
标题翻译：带有数字数据线的存储器及其制造方法
公开(公告)号：US20110220980A1
公开(公告)日：2011-09-15
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

5. 发明授权

US06342670B1 Photoelectric module device 有权
标题翻译：光电模块设备
公开(公告)号：US06342670B1
公开(公告)日：2002-01-29
申请号：US09664780
申请日：2000-09-19
申请人： Ching Kai Lin , Hsu Keng Tseng
发明人： Ching Kai Lin , Hsu Keng Tseng
IPC分类号： H01L31048
CPC分类号： H01L31/0203 , G08C23/04 , H01L31/02327 , H01L31/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/1815 , Y10S136/293 , Y10S362/80 , Y10S428/901 , H01L2924/00014
摘要： A photoelectric module device comprising a multiple layer printed circuit board and at least one photoelectric module device is provided. The multiple layer printed circuit board has at least an upper circuit board substrate, a lower circuit board substrate, and a circuit. A plurality of photoelectric elements are installed on the multiple layer printed circuit board and is electrically connected to the circuit. The photoelectric elements are packaged above the multiple layer printed circuit board by injection molding a transparent resin thereon. The lower substrate has a plurality of through holes formed therein and the inner wall of the through holes is plated with metal, as an electric terminal. The upper circuit board substrate serves to seal the through holes and prevent resin from permeating therein during the injection molding process. When the circuit board is cut into separate photoelectric module devices, after packaging, the inner wall of the through holes are partially cut away and the remaining portion thereof becomes a terminal for electrically connecting to external devices.
摘要翻译：提供一种包括多层印刷电路板和至少一个光电模块装置的光电模块装置。多层印刷电路板至少具有上电路板基板，下电路板基板和电路。多个光电元件安装在多层印刷电路板上，并与电路电连接。光电元件通过在其上注塑成型透明树脂而封装在多层印刷电路板的上方。下基板具有形成在其中的多个通孔，并且通孔的内壁镀有金属作为电端子。上部电路板基板用于密封通孔，并防止树脂在注射成型过程中渗入其中。当将电路板切割成单独的光电模块装置时，在封装之后，通孔的内壁被部分地切除，其余部分变成用于电连接到外部装置的端子。

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