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1. 发明授权

US09977674B2 Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction 有权
公开(公告)号：US09977674B2
公开(公告)日：2018-05-22
申请号：US10685654
申请日：2003-10-14
申请人： Jeffrey P. Rupley, II , Edward A. Brekelbaum , Edward T. Grochowski , Bryan P. Black
发明人： Jeffrey P. Rupley, II , Edward A. Brekelbaum , Edward T. Grochowski , Bryan P. Black
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

2. 发明授权

US07171545B2 Predictive filtering of register cache entry 有权
标题翻译：寄存器缓存条目的预测过滤
公开(公告)号：US07171545B2
公开(公告)日：2007-01-30
申请号：US10747625
申请日：2003-12-30
申请人： John P. Devale , Bryan P. Black , Edward A. Brekelbaum , Jeffrey P. Rupley, II
发明人： John P. Devale , Bryan P. Black , Edward A. Brekelbaum , Jeffrey P. Rupley, II
IPC分类号： G06F9/30
CPC分类号： G06F9/30138
摘要： A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.
摘要翻译：支持预测寄存器高速缓存分配和输入的机制使用计数器查找表来确定物理寄存器引用的潜在重要性。

3. 发明授权

US07130990B2 Efficient instruction scheduling with lossy tracking of scheduling information 失效
标题翻译：有效的指令调度与有序的跟踪调度信息
公开(公告)号：US07130990B2
公开(公告)日：2006-10-31
申请号：US10334528
申请日：2002-12-31
申请人： Edward A. Brekelbaum , Bryan P. Black , Jeffrey P. Rupley, II
发明人： Edward A. Brekelbaum , Bryan P. Black , Jeffrey P. Rupley, II
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.
摘要翻译：提供了一种用于向调度器提供就绪信息的方法和装置。依赖信息保存在相对较小的地图表中，当依赖信息超过地图表中的可用空间时，可能会丢失信息。在选择队列中，随着空间允许，维护就绪指令。调度指令的标签保存在查找队列中，并且随着空间允许，调度指令的依赖关系信息保持在更新队列中。基于更新队列中的信息更新调度窗口中的指令的就绪信息。由于空间限制，映射表，查找队列，更新队列和/或选择队列可能会导致指令信息丢失。丢失指令的调度由有损指令处理程序处理。

4. 发明授权

US07428631B2 Apparatus and method using different size rename registers for partial-bit and bulk-bit writes 有权
标题翻译：使用不同大小的重命名寄存器进行部分位和批量位写入的装置和方法
公开(公告)号：US07428631B2
公开(公告)日：2008-09-23
申请号：US10632432
申请日：2003-07-31
申请人： Jeffrey P. Rupley, II , Edward A. Brekelbaum , Bryan P. Black
发明人： Jeffrey P. Rupley, II , Edward A. Brekelbaum , Bryan P. Black
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/384
摘要： An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.
摘要翻译：提供了一种装置和方法，用于重命名允许不同长度的比特访问的逻辑寄存器，例如谓词寄存器。重命名逻辑支持对部分位访问和对寄存器的位的批量访问进行重命名。重命名逻辑利用与逻辑寄存器相关联的重命名映射表来重命名，并且还包括多个物理重命名寄存器。它们的物理重命名寄存器包括一组用于部分位写入重命名的瘦物理重命名寄存器。物理重命名寄存器还包括一组用于批量位写入重命名的胖物理重命名寄存器。还可以使用附加大小的物理重命名寄存器。单个物理重命名映射表的条目可能指向胖或瘦身体重命名寄存器。

5. 发明授权

US07418551B2 Multi-purpose register cache 有权
标题翻译：多用途寄存器缓存
公开(公告)号：US07418551B2
公开(公告)日：2008-08-26
申请号：US10886402
申请日：2004-07-06
申请人： John P. DeVale , Bryan P. Black , Edward A. Brekelbaum , Jeffrey P. Rupley, II
发明人： John P. DeVale , Bryan P. Black , Edward A. Brekelbaum , Jeffrey P. Rupley, II
IPC分类号： G06F12/00
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F12/0875 , Y02D10/13
摘要： A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.
摘要翻译：如果注册文件资源不可用，则使用可用的注册缓存资源的技术。如果寄存器文件写入端口或空间不可用，本发明的实施例涉及用于将写回数据存储到寄存器高速缓存的寄存器高速缓存回写算法。

6. 发明授权

US08110899B2 Method for incorporating existing silicon die into 3D integrated stack 有权
标题翻译：将现有硅晶片并入3D集成堆叠的方法
公开(公告)号：US08110899B2
公开(公告)日：2012-02-07
申请号：US11613774
申请日：2006-12-20
申请人： Paul A. Reed , Bryan P. Black
发明人： Paul A. Reed , Bryan P. Black
IPC分类号： H01L23/48
CPC分类号： H01L25/0652 , H01L23/481 , H01L25/18 , H01L2224/0401 , H01L2224/06156 , H01L2224/13025 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.
摘要翻译：一种包括包括多个导电通过基板通孔（TSV））的第一管芯的装置; 以及多个第二骰子，每个第二骰子都包括耦合到第一骰子的TSV的多个接触点，所述多个第二骰子被布置成集体地包括接近第一骰子的表面积的表面积。一种方法，包括在第一管芯上布置多个第二管芯，使得多个第二管芯集体包括接近第一管芯表面积的表面积; 以及将多个第二装置电耦合到多个第一管芯。一种包括包括印刷电路板和模块的电子设备的系统，所述模块包括包括多个TSV的第一裸片; 并且所述多个第二管芯被布置成共同地包括接近所述第一管芯的表面积的表面积。

7. 发明申请

US20080150088A1 METHOD FOR INCORPORATING EXISTING SILICON DIE INTO 3D INTEGRATED STACK 有权
标题翻译：将现有硅芯片并入3D集成堆叠的方法
公开(公告)号：US20080150088A1
公开(公告)日：2008-06-26
申请号：US11613774
申请日：2006-12-20
申请人： Paul A. Reed , Bryan P. Black
发明人： Paul A. Reed , Bryan P. Black
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/0652 , H01L23/481 , H01L25/18 , H01L2224/0401 , H01L2224/06156 , H01L2224/13025 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.
摘要翻译：一种包括包括多个导电通过基板通孔（TSV））的第一管芯的装置; 以及多个第二骰子，每个第二骰子都包括耦合到第一骰子的TSV的多个接触点，所述多个第二骰子被布置成集体地包括接近第一骰子的表面积的表面积。一种方法，包括在第一管芯上布置多个第二管芯，使得多个第二管芯集体包括接近第一管芯表面积的表面积; 以及将多个第二装置电耦合到多个第一管芯。一种包括包括印刷电路板和模块的电子设备的系统，所述模块包括包括多个TSV的第一裸片; 并且所述多个第二管芯被布置成共同地包括接近所述第一管芯的表面积的表面积。

8. 发明申请

US20090138688A1 Multi-Die Processor 有权
标题翻译：多模处理器
公开(公告)号：US20090138688A1
公开(公告)日：2009-05-28
申请号：US12365171
申请日：2009-02-04
申请人： Bryan P. Black , Nicholas G. Samra , M. Clair Webb
发明人： Bryan P. Black , Nicholas G. Samra , M. Clair Webb
IPC分类号： G06F9/38
CPC分类号： G06F15/7832 , H01L24/16 , H01L25/0657 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/73253 , H01L2225/06513 , H01L2225/06562 , H01L2225/06565 , H01L2924/00013 , H01L2924/14 , Y02D10/12 , Y02D10/13 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00 , H01L2924/00014
摘要： Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.
摘要翻译：公开了一种多芯片处理器装置和系统。执行一个或多个指令的处理器逻辑在两个或多个面对面堆叠的骰子之间分配。处理器包括在堆叠的骰子之间的导电接口，以便于管芯到管芯的通信。

9. 发明授权

US5761723A Data processor with branch prediction and method of operation 失效
标题翻译：具有分支预测和操作方法的数据处理器
公开(公告)号：US5761723A
公开(公告)日：1998-06-02
申请号：US637189
申请日：1996-04-08
申请人： Bryan P. Black , Marvin Denman , Mark A. Kearney , Seungyoon Peter Song
发明人： Bryan P. Black , Marvin Denman , Mark A. Kearney , Seungyoon Peter Song
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3861
摘要： A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.
摘要翻译：数据处理器（10）具有分支目标地址高速缓冲存储器（48），用于存储多个最近采取的分支指令的目标地址。通常，将每个获取地址与分支目标地址高速缓存的内容进行比较。如果发生命中，则数据处理器分支到缓存的目标地址。数据处理器还具有一个调度单元（60），当分支目标地址缓存器确定分支目标地址高速缓冲存储器“完全不是分支指令”的指令时，使分配目标地址缓存中存储的数据无效，幻影分支“。因此，数据处理器在上下文切换之后自动使其分支目标地址高速缓存数据失效。

10. 发明授权

US5613081A Method of operating a data processor with rapid address comparison for data forwarding 失效
标题翻译：用于数据转发的快速地址比较操作数据处理器的方法
公开(公告)号：US5613081A
公开(公告)日：1997-03-18
申请号：US526398
申请日：1995-09-11
申请人： Bryan P. Black , Marvin A. Denman
发明人： Bryan P. Black , Marvin A. Denman
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3802 , G06F12/0859
摘要： A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.
摘要翻译：数据处理器（10）具有用于产生每个请求数据双字的地址的执行单元（18,20）。数据处理器在数据处理器的存储器高速缓存中未找到所请求的双字时，提取整个存储器行，四个双字数据，其中包含所请求的双字。当从外部存储器系统返回时，数据处理器最终将所请求的数据存储在存储器高速缓存（40）中。数据处理器还具有用于在某些情况下将先前请求的双字直接转发到执行单元的转发电路（48,50）。如果数据处理器自上次存储器高速缓存未命中以来没有超过存储器线边界，并且所请求和接收的双字的两个最低有效位逻辑上匹配，转发电路将转发所请求的双字。

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