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1. 发明授权

US07707396B2 Data processing system, processor and method of data processing having improved branch target address cache 失效
标题翻译：数据处理系统，处理器和数据处理方法具有改进的分支目标地址缓存
公开(公告)号：US07707396B2
公开(公告)日：2010-04-27
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

2. 发明申请

US20080120496A1 Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache 失效
标题翻译：数据处理系统，具有改进的分支目标地址缓存的数据处理的处理器和方法
公开(公告)号：US20080120496A1
公开(公告)日：2008-05-22
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

3. 发明授权

US08358503B2 Stackable module for energy-efficient computing systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US08358503B2
公开(公告)日：2013-01-22
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： H05K7/20
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

4. 发明授权

US08179674B2 Scalable space-optimized and energy-efficient computing system 失效
标题翻译：可扩展的空间优化和节能计算系统
公开(公告)号：US08179674B2
公开(公告)日：2012-05-15
申请号：US12789583
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, Jr. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , H05K7/20
CPC分类号： G06F1/20
摘要： A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
摘要翻译：提供了可扩展的空间优化和节能计算系统。计算系统包括在六排配置中配置的框架的至少一个级别中的多个模块化隔间。计算系统还包括空气入口，空气混合增压室和至少一个风扇。在计算系统中，多个模块化隔间固定在空气入口上方，空气混合气室固定在多个模块化隔间上方，并且至少一个风扇固定在空气混合气室的上方。当至少一个模块被插入多个模块化隔间中的一个时，模块耦合到框架内的背板。

5. 发明申请

US20110292594A1 Scalable Space-Optimized and Energy-Efficient Computing System 失效
标题翻译：可扩展空间优化和节能计算系统
公开(公告)号：US20110292594A1
公开(公告)日：2011-12-01
申请号：US12789583
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Jian Li , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： G06F1/20
摘要： A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame.
摘要翻译：提供了可扩展的空间优化和节能计算系统。计算系统包括在六排配置中配置的框架的至少一个级别中的多个模块化隔间。计算系统还包括空气入口，空气混合增压室和至少一个风扇。在计算系统中，多个模块化隔间固定在空气入口上方，空气混合气室固定在多个模块化隔间上方，并且至少一个风扇固定在空气混合气室的上方。当至少一个模块被插入多个模块化隔间中的一个时，模块耦合到框架内的背板。

6. 发明申请

US20070283101A1 Just-In-Time Prefetching 失效
标题翻译：即时预取
公开(公告)号：US20070283101A1
公开(公告)日：2007-12-06
申请号：US11422459
申请日：2006-06-06
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
摘要翻译：一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求）使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

7. 发明申请

US20110292597A1 Stackable Module for Energy-Efficient Computing Systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US20110292597A1
公开(公告)日：2011-12-01
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

8. 发明授权

US07487297B2 Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system 失效
标题翻译：动态调整预取距离，以便在处理系统中实现即时预取
公开(公告)号：US07487297B2
公开(公告)日：2009-02-03
申请号：US11422459
申请日：2006-06-06
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862
摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
摘要翻译：一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求）使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

9. 发明申请

US20080016330A1 Efficient Multiple-Table Reference Prediction Mechanism 失效
标题翻译：高效多表参考预测机制
公开(公告)号：US20080016330A1
公开(公告)日：2008-01-17
申请号：US11457178
申请日：2006-07-13
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F9/44
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0897 , G06F2212/6026
摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.
摘要翻译：一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。在预取引擎（或与其相关联）中提供了多个（简单）历史表。多个表中的每一个用于检测不同的访问模式。这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

10. 发明授权

US07657729B2 Efficient multiple-table reference prediction mechanism 失效
标题翻译：高效多表参考预测机制
公开(公告)号：US07657729B2
公开(公告)日：2010-02-02
申请号：US11457178
申请日：2006-07-13
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0897 , G06F2212/6026
摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.
摘要翻译：一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。在预取引擎（或与其相关联）中提供了多个（简单）历史表。多个表中的每一个用于检测不同的访问模式。这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

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