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1. 发明申请

US20090210665A1 System and Method for a Group Priority Issue Schema for a Cascaded Pipeline 失效
标题翻译：用于级联管道的组优先级问题模式的系统和方法
公开(公告)号：US20090210665A1
公开(公告)日：2009-08-20
申请号：US12033038
申请日：2008-02-19
申请人： Jeffrey P. Bradford , David A. Luick
发明人： Jeffrey P. Bradford , David A. Luick
IPC分类号： G06F9/312
CPC分类号： G06F9/3814 , G06F9/382 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3853 , G06F9/3869 , G06F9/3889
摘要： The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to receiving an issue group of instructions, reordering the issue group of instructions using instruction type priority, and executing the reordered issue group of instructions in the cascaded delayed execution pipeline unit. The method, among others, can be broadly summarized by the following steps: receiving an issue group of instructions, reordering the issue group of instructions using instruction type priority, and executing the reordered issue group of instructions in the cascaded delayed execution pipeline unit.
摘要翻译：本发明提供了用于级联管道的组优先级问题模式的系统和方法。该系统包括具有多个执行流水线的级联延迟执行流水线单元，该多个执行流水线以相对于彼此的延迟方式在公共问题组中执行指令。该系统还包括被配置为接收问题组指令，使用指令类型优先级重新排序指令类型的指令的电路，以及在级联延迟执行流水线单元中执行重新排序的指令组。该方法可以通过以下步骤大致概括：接收问题组指令，使用指令类型优先级重新排序指令的使用组，以及在级联延迟执行流水线单元中执行重新排序的指令组。

2. 发明申请

US20090043995A1 Handling Data Cache Misses Out-of-Order for Asynchronous Pipelines 有权
标题翻译：异步管道处理数据缓存失败
公开(公告)号：US20090043995A1
公开(公告)日：2009-02-12
申请号：US12253448
申请日：2008-10-17
申请人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
发明人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： An apparatus and method for handling data cache misses out-of-order for asynchronous pipelines are provided. The apparatus and method associates load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
摘要翻译：提供了一种用于处理数据高速缓存的装置和方法，其中异步管线的次序不正常。该装置和方法将加载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。当加载指令发出并看到其在负载表中的对应条目标记为“未命中”时，取消加载指令的发布效果，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时所需数据被回收。

3. 发明授权

US07461239B2 Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines 失效
标题翻译：用于处理数据高速缓存的装置和方法对于异步管线错过无序
公开(公告)号：US07461239B2
公开(公告)日：2008-12-02
申请号：US11345922
申请日：2006-02-02
申请人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
发明人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
IPC分类号： G06F12/00 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
摘要翻译：提供了处理异步管道数据高速缓存未命中的机制。这些机制将负载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。当加载指令发出并看到其在负载表中的相应条目标记为“未命中”时，发出加载指令的影响被取消，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时所需数据被回收。

4. 发明授权

US07454602B2 Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group 失效
标题翻译：管道具有分叉全局分支历史缓冲区，用于每个指令获取组索引分支历史表
公开(公告)号：US07454602B2
公开(公告)日：2008-11-18
申请号：US11013148
申请日：2004-12-15
申请人： Chris M. Abernathy , Jeffrey P. Bradford , Jason N. Dale , Timothy H. Heil
发明人： Chris M. Abernathy , Jeffrey P. Bradford , Jason N. Dale , Timothy H. Heil
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a group of the most recent branch instructions. The branch history table includes multiple entries, each entry is associated with one or more branch instructions. The GBH information from the GBH buffer can be used to index into the branch history table to obtain a branch prediction signal. In response to a fetch group of instructions, a fixed number of GBH bits is shifted into the GBH buffer. The number of GBH bits is the same regardless of the number of branch instructions within the fetch group of instructions. In addition, there is a unique bit pattern associated with the case of no taken branch in the fetch group, regardless of the number of not-taken branches of even if there are any branches in the fetch group.
摘要翻译：公开了一种用于更新全局分支历史信息的方法和装置。数据处理系统中的动态分支预测器包括全局分支历史（GBH）缓冲区和分支历史表。 GBH缓冲区包含一组最新分支指令的GBH信息。分支历史表包括多个条目，每个条目与一个或多个分支指令相关联。来自GBH缓冲器的GBH信息可以用于索引到分支历史表中以获得分支预测信号。响应于取指令组，固定数量的GBH位被移入GBH缓冲器。无论读取指令组中的分支指令数如何，GBH位数都是相同的。另外，即使在取出组中有任何分支，也不管抽取分支的数目如何，与获取组中没有分支的情况相关联的唯一位模式。

5. 发明授权

US08108654B2 System and method for a group priority issue schema for a cascaded pipeline 失效
标题翻译：用于级联管道的组优先级问题模式的系统和方法
公开(公告)号：US08108654B2
公开(公告)日：2012-01-31
申请号：US12033038
申请日：2008-02-19
申请人： Jeffrey P. Bradford , David A. Luick
发明人： Jeffrey P. Bradford , David A. Luick
IPC分类号： G06F9/40
CPC分类号： G06F9/3814 , G06F9/382 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3853 , G06F9/3869 , G06F9/3889
摘要： The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to receiving an issue group of instructions, reordering the issue group of instructions using instruction type priority, and executing the reordered issue group of instructions in the cascaded delayed execution pipeline unit. The method, among others, can be broadly summarized by the following steps: receiving an issue group of instructions, reordering the issue group of instructions using instruction type priority, and executing the reordered issue group of instructions in the cascaded delayed execution pipeline unit.
摘要翻译：本发明提供了用于级联管道的组优先级问题模式的系统和方法。该系统包括具有多个执行流水线的级联延迟执行流水线单元，该多个执行流水线以相对于彼此的延迟方式在公共问题组中执行指令。该系统还包括被配置为接收问题组指令，使用指令类型优先级重新排序指令类型的指令的电路，以及在级联延迟执行流水线单元中执行重新排序的指令组。该方法可以通过以下步骤大致概括：接收问题组指令，使用指令类型优先级重新排序指令的使用组，以及在级联延迟执行流水线单元中执行重新排序的指令组。

6. 发明授权

US07900024B2 Handling data cache misses out-of-order for asynchronous pipelines 有权
标题翻译：异步管道处理数据高速缓存无序乱序
公开(公告)号：US07900024B2
公开(公告)日：2011-03-01
申请号：US12253448
申请日：2008-10-17
申请人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
发明人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
摘要翻译：提供了处理异步管道数据高速缓存未命中的机制。这些机制将负载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。当加载指令发出并看到其在负载表中的相应条目标记为“未命中”时，发出加载指令的影响被取消，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时所需数据被回收。

7. 发明授权

US07707396B2 Data processing system, processor and method of data processing having improved branch target address cache 失效
标题翻译：数据处理系统，处理器和数据处理方法具有改进的分支目标地址缓存
公开(公告)号：US07707396B2
公开(公告)日：2010-04-27
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

8. 发明授权

US07453798B2 Active flow management with hysteresis 失效
标题翻译：主动流量管理带滞后
公开(公告)号：US07453798B2
公开(公告)日：2008-11-18
申请号：US10782617
申请日：2004-02-19
申请人： Jeffrey P. Bradford , Gordon T. Davis , Dongming Hwang , Clark D. Jeffries , Srinivasan Ramani , Kartik Sudeep , Ken V. Vu
发明人： Jeffrey P. Bradford , Gordon T. Davis , Dongming Hwang , Clark D. Jeffries , Srinivasan Ramani , Kartik Sudeep , Ken V. Vu
IPC分类号： H04L12/00
CPC分类号： H04L47/10 , H04L47/29 , H04L47/323
摘要： The present invention provides for a computer network method and system that applies “hysteresis” to an active queue management algorithm. If a queue is at a level below a certain low threshold and a burst of packets arrives at a network node, then the probability of dropping the initial packets in the burst is recalculated, but the packets are not dropped. However, if the queue level crosses beyond a hysteresis threshold, then packets are discarded pursuant to a drop probability.Also, according to the present invention, queue level may be decreased until it becomes less than the hysteresis threshold, with packets dropped per the drop probability until the queue level decreases to at least a low threshold. In one embodiment, an adaptive algorithm is also provided to adjust the transmit probability for each flow together with hysteresis to increase the packet transmit rates to absorb bursty traffic.
摘要翻译：本发明提供一种向活动队列管理算法应用“迟滞”的计算机网络方法和系统。如果队列处于低于某个低阈值的水平，并且一群数据包到达网络节点，则重新计算突发中丢弃初始数据包的概率，但不会丢弃数据包。然而，如果队列级别超过滞后阈值，则根据丢弃概率丢弃数据包。此外，根据本发明，可以减少队列级别，直到其变得小于滞后阈值，其中每个丢弃概率的分组丢弃，直到队列级别降低到至少低阈值。在一个实施例中，还提供自适应算法来调整每个流的发送概率以及迟滞以增加分组传输速率以吸收突发业务。

9. 发明申请

US20080120496A1 Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache 失效
标题翻译：数据处理系统，具有改进的分支目标地址缓存的数据处理的处理器和方法
公开(公告)号：US20080120496A1
公开(公告)日：2008-05-22
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

10. 发明申请

US20070288731A1 Dual Path Issue for Conditional Branch Instructions 审中-公开
标题翻译：有条件分支指令的双路径问题
公开(公告)号：US20070288731A1
公开(公告)日：2007-12-13
申请号：US11422905
申请日：2006-06-08
申请人： Jeffrey P. Bradford , David A. Luick
发明人： Jeffrey P. Bradford , David A. Luick
IPC分类号： G06F15/00
CPC分类号： G06F9/3804 , G06F9/30072 , G06F9/382 , G06F9/3828 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3869 , G06F9/3889
摘要： A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction and issuing one or more instructions from a first path of the branch instruction and one or more instructions from a second path of the branch instruction. If the first path of the branch instruction is followed by the branch instruction, the one or more instructions from the second path of the branch instruction are invalidated. If the second path of the branch instruction is followed by the branch instruction, the one or more instructions from the first path of the branch instruction are invalidated.
摘要翻译：提供一种用于执行分支指令的方法和装置。在一个实施例中，该方法包括从分支指令的第一路径接收分支指令和发出一个或多个指令以及来自分支指令的第二路径的一个或多个指令。如果分支指令的第一路径跟随分支指令，则来自分支指令的第二路径的一个或多个指令无效。如果分支指令的第二路径后面是分支指令，则来自分支指令的第一路径的一个或多个指令无效。

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